2 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
4 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/system.h>
13 #include <asm/arch/cpu.h>
14 #include <asm/arch/soc.h>
15 #include <asm/armv8/mmu.h>
17 DECLARE_GLOBAL_DATA_PTR;
20 #define MVEBU_GPIO_NB_REG_BASE (MVEBU_REGISTER(0x13800))
22 #define MVEBU_TEST_PIN_LATCH_N (MVEBU_GPIO_NB_REG_BASE + 0x8)
23 #define MVEBU_XTAL_MODE_MASK BIT(9)
24 #define MVEBU_XTAL_MODE_OFFS 9
25 #define MVEBU_XTAL_CLOCK_25MHZ 0x0
26 #define MVEBU_XTAL_CLOCK_40MHZ 0x1
28 #define MVEBU_NB_WARM_RST_REG (MVEBU_GPIO_NB_REG_BASE + 0x40)
29 #define MVEBU_NB_WARM_RST_MAGIC_NUM 0x1d1e
31 static struct mm_region mvebu_mem_map[] = {
37 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
41 /* SRAM, MMIO regions */
44 .size = 0x02000000UL, /* 32MiB internal registers */
45 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
54 struct mm_region *mem_map = mvebu_mem_map;
56 void reset_cpu(ulong ignored)
59 * Write magic number of 0x1d1e to North Bridge Warm Reset register
60 * to trigger warm reset
62 writel(MVEBU_NB_WARM_RST_MAGIC_NUM, MVEBU_NB_WARM_RST_REG);
68 * return: reference clock in MHz (25 or 40)
74 regval = (readl(MVEBU_TEST_PIN_LATCH_N) & MVEBU_XTAL_MODE_MASK) >>
77 if (regval == MVEBU_XTAL_CLOCK_25MHZ)