3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6 * Header file for the Marvell's Feroceon CPU core.
8 * SPDX-License-Identifier: GPL-2.0+
14 #define SOC_MV78460_ID 0x7846
15 #define SOC_88F6810_ID 0x6810
16 #define SOC_88F6820_ID 0x6820
17 #define SOC_88F6828_ID 0x6828
20 #define MV_88F68XX_Z1_ID 0x0
21 #define MV_88F68XX_A0_ID 0x4
23 /* TCLK Core Clock definition */
24 #ifndef CONFIG_SYS_TCLK
25 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */
28 /* SOC specific definations */
29 #define INTREG_BASE 0xd0000000
30 #define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080)
31 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SYS_MVEBU_DDR_A38X)
33 * On A38x switching the regs base address without running from
34 * SDRAM doesn't seem to work. So let the SPL still use the
35 * default base address and switch to the new address in the
38 #define SOC_REGS_PHY_BASE 0xd0000000
40 #define SOC_REGS_PHY_BASE 0xf1000000
42 #define MVEBU_REGISTER(x) (SOC_REGS_PHY_BASE + x)
44 #define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504))
45 #define MVEBU_L2_CACHE_BASE (MVEBU_REGISTER(0x08000))
46 #define CONFIG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE
47 #define MVEBU_SPI_BASE (MVEBU_REGISTER(0x10600))
48 #define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000))
49 #define MVEBU_UART0_BASE (MVEBU_REGISTER(0x12000))
50 #define MVEBU_UART1_BASE (MVEBU_REGISTER(0x12100))
51 #define MVEBU_MPP_BASE (MVEBU_REGISTER(0x18000))
52 #define MVEBU_GPIO0_BASE (MVEBU_REGISTER(0x18100))
53 #define MVEBU_GPIO1_BASE (MVEBU_REGISTER(0x18140))
54 #define MVEBU_GPIO2_BASE (MVEBU_REGISTER(0x18180))
55 #define MVEBU_SYSTEM_REG_BASE (MVEBU_REGISTER(0x18200))
56 #define MVEBU_CPU_WIN_BASE (MVEBU_REGISTER(0x20000))
57 #define MVEBU_SDRAM_BASE (MVEBU_REGISTER(0x20180))
58 #define MVEBU_TIMER_BASE (MVEBU_REGISTER(0x20300))
59 #define MVEBU_EGIGA2_BASE (MVEBU_REGISTER(0x30000))
60 #define MVEBU_EGIGA3_BASE (MVEBU_REGISTER(0x34000))
61 #define MVEBU_REG_PCIE_BASE (MVEBU_REGISTER(0x40000))
62 #define MVEBU_USB20_BASE (MVEBU_REGISTER(0x58000))
63 #define MVEBU_EGIGA0_BASE (MVEBU_REGISTER(0x70000))
64 #define MVEBU_EGIGA1_BASE (MVEBU_REGISTER(0x74000))
65 #define MVEBU_AXP_SATA_BASE (MVEBU_REGISTER(0xa0000))
66 #define MVEBU_SATA0_BASE (MVEBU_REGISTER(0xa8000))
67 #define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000))
69 #define SDRAM_MAX_CS 4
70 #define SDRAM_ADDR_MASK 0xFF000000
72 /* MVEBU CPU memory windows */
73 #define MVCPU_WIN_CTRL_DATA CPU_WIN_CTRL_DATA
74 #define MVCPU_WIN_ENABLE CPU_WIN_ENABLE
75 #define MVCPU_WIN_DISABLE CPU_WIN_DISABLE
77 #endif /* _MVEBU_SOC_H */