2 * Copyright (C) Marvell International Ltd. and its affiliates
4 * SPDX-License-Identifier: GPL-2.0
11 #include <asm/arch/cpu.h>
12 #include <asm/arch/soc.h>
14 #include "high_speed_env_spec.h"
15 #include "board_env_spec.h"
17 #define SERDES_VERION "2.1.5"
18 #define ENDED_OK "High speed PHY - Ended Successfully\n"
20 static const u8 serdes_cfg[][SERDES_LAST_UNIT] = BIN_SERDES_CFG;
22 extern MV_BIN_SERDES_CFG *serdes_info_tbl[];
24 extern u8 rd78460gp_twsi_dev[];
25 extern u8 db88f78xx0rev2_twsi_dev[];
27 u32 pex_cfg_read(u32 pex_if, u32 bus, u32 dev, u32 func, u32 offs);
28 int pex_local_bus_num_set(u32 pex_if, u32 bus_num);
29 int pex_local_dev_num_set(u32 pex_if, u32 dev_num);
31 #define MV_BOARD_PEX_MODULE_ADDR 0x23
32 #define MV_BOARD_PEX_MODULE_ID 1
33 #define MV_BOARD_ETM_MODULE_ID 2
35 #define PEX_MODULE_DETECT 1
36 #define ETM_MODULE_DETECT 2
38 #define PEX_MODE_GET(satr) ((satr & 0x6) >> 1)
39 #define PEX_CAPABILITY_GET(satr) (satr & 1)
40 #define MV_PEX_UNIT_TO_IF(pex_unit) ((pex_unit < 3) ? (pex_unit * 4) : 9)
42 /* Static parametes */
43 static int config_module;
44 static int switch_module;
47 static u32 board_id_get(void)
49 #if defined(CONFIG_DB_88F78X60)
50 return DB_88F78XX0_BP_ID;
51 #elif defined(CONFIG_RD_88F78460_SERVER)
52 return RD_78460_SERVER_ID;
53 #elif defined(CONFIG_RD_78460_SERVER_REV2)
54 return RD_78460_SERVER_REV2_ID;
55 #elif defined(CONFIG_DB_78X60_PCAC)
56 return DB_78X60_PCAC_ID;
57 #elif defined(CONFIG_DB_88F78X60_REV2)
58 return DB_88F78XX0_BP_REV2_ID;
59 #elif defined(CONFIG_RD_78460_NAS)
60 return RD_78460_NAS_ID;
61 #elif defined(CONFIG_DB_78X60_AMC)
62 return DB_78X60_AMC_ID;
63 #elif defined(CONFIG_DB_78X60_PCAC_REV2)
64 return DB_78X60_PCAC_REV2_ID;
65 #elif defined(CONFIG_DB_784MP_GP)
66 return DB_784MP_GP_ID;
67 #elif defined(CONFIG_RD_78460_CUSTOMER)
68 return RD_78460_CUSTOMER_ID;
71 * Return 0 here for custom board as this should not be used
78 __weak u8 board_sat_r_get(u8 dev_num, u8 reg)
82 u32 board_id = board_id_get();
87 case DB_78X60_PCAC_REV2_ID:
88 case RD_78460_CUSTOMER_ID:
89 case RD_78460_SERVER_ID:
90 case RD_78460_SERVER_REV2_ID:
91 case DB_78X60_PCAC_ID:
92 return (0x1 << 1) | 1;
93 case FPGA_88F78XX0_ID:
95 return (0x0 << 1) | 1;
97 dev = rd78460gp_twsi_dev;
100 case DB_88F78XX0_BP_ID:
101 case DB_88F78XX0_BP_REV2_ID:
102 dev = db88f78xx0rev2_twsi_dev;
109 /* Read MPP module ID */
110 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
111 ret = i2c_read(dev[dev_num], 0, 1, (u8 *)&data, 1);
118 static int board_modules_scan(void)
121 u32 board_id = board_id_get();
124 /* Perform scan only for DB board */
125 if ((board_id == DB_88F78XX0_BP_ID) ||
126 (board_id == DB_88F78XX0_BP_REV2_ID)) {
127 /* reset modules flags */
130 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
132 /* SERDES module (only PEX model is supported now) */
133 ret = i2c_read(MV_BOARD_PEX_MODULE_ADDR, 0, 1, (u8 *)&val, 1);
137 if (val == MV_BOARD_PEX_MODULE_ID)
138 config_module = PEX_MODULE_DETECT;
139 if (val == MV_BOARD_ETM_MODULE_ID)
140 config_module = ETM_MODULE_DETECT;
141 } else if (board_id == RD_78460_NAS_ID) {
143 if ((reg_read(GPP_DATA_IN_REG(2)) & MV_GPP66) == 0x0)
150 u32 pex_max_unit_get(void)
154 * Right now only MV78460 is supported. Other SoC's might need
155 * a different value here.
157 return MV_PEX_MAX_UNIT;
160 u32 pex_max_if_get(void)
164 * Right now only MV78460 is supported. Other SoC's might need
165 * a different value here.
167 return MV_PEX_MAX_IF;
170 u8 board_cpu_freq_get(void)
175 sar = reg_read(MPP_SAMPLE_AT_RESET(0));
176 sar_msb = reg_read(MPP_SAMPLE_AT_RESET(1));
177 return ((sar_msb & 0x100000) >> 17) | ((sar & 0xe00000) >> 21);
180 __weak MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode)
183 u32 serdes_cfg_val = 0; /* default */
185 board_id = board_id_get();
193 return &serdes_info_tbl[board_id - BOARD_ID_BASE][serdes_cfg_val];
196 u16 ctrl_model_get(void)
199 * SoC version can't be autodetected. So we need to rely on a define
200 * from the config system here.
202 #ifdef CONFIG_MV78260
203 return MV_78260_DEV_ID;
205 return MV_78460_DEV_ID;
209 u32 get_line_cfg(u32 line_num, MV_BIN_SERDES_CFG *info)
212 return (info->line0_7 >> (line_num << 2)) & 0xF;
214 return (info->line8_15 >> ((line_num - 8) << 2)) & 0xF;
217 static int serdes_max_lines_get(void)
219 switch (ctrl_model_get()) {
220 case MV_78260_DEV_ID:
222 case MV_78460_DEV_ID:
229 int serdes_phy_config(void)
234 /* addr/value for each line @ every setup step */
235 u32 addr[16][11], val[16][11];
236 u8 pex_unit, pex_line_num;
241 MV_BIN_SERDES_CFG *info;
246 u32 rx_high_imp_mode;
252 * Get max. serdes lines count
254 max_serdes_lines = serdes_max_lines_get();
255 if (max_serdes_lines == 0)
258 satr11 = board_sat_r_get(1, 1);
259 if ((u8) MV_ERROR == (u8) satr11)
262 board_modules_scan();
263 memset(addr, 0, sizeof(addr));
264 memset(val, 0, sizeof(val));
266 /* Check if DRAM is already initialized */
267 if (reg_read(REG_BOOTROM_ROUTINE_ADDR) &
268 (1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS)) {
269 DEBUG_INIT_S("High speed PHY - Version: ");
270 DEBUG_INIT_S(SERDES_VERION);
271 DEBUG_INIT_S(" - 2nd boot - Skip\n");
274 DEBUG_INIT_S("High speed PHY - Version: ");
275 DEBUG_INIT_S(SERDES_VERION);
276 DEBUG_INIT_S(" (COM-PHY-V20)\n");
279 * AVS : disable AVS for frequency less than 1333
281 freq = board_cpu_freq_get();
282 device_rev = mv_ctrl_rev_get();
284 if (device_rev == 2) { /* for B0 only */
287 cpu_avs = reg_read(CPU_AVS_CONTROL2_REG);
288 DEBUG_RD_REG(CPU_AVS_CONTROL2_REG, cpu_avs);
289 cpu_avs &= ~(1 << 9);
291 if ((0x4 == freq) || (0xB == freq)) {
294 tmp2 = reg_read(CPU_AVS_CONTROL0_REG);
295 DEBUG_RD_REG(CPU_AVS_CONTROL0_REG, tmp2);
296 /* cpu upper limit = 1.1V cpu lower limit = 0.9125V */
298 reg_write(CPU_AVS_CONTROL0_REG, tmp2);
299 DEBUG_WR_REG(CPU_AVS_CONTROL0_REG, tmp2);
300 cpu_avs |= (1 << 9); /* cpu avs enable */
301 cpu_avs |= (1 << 18); /* AvsAvddDetEn enable */
302 fabric_freq = (reg_read(MPP_SAMPLE_AT_RESET(0)) &
303 SAR0_FABRIC_FREQ_MASK) >> SAR0_FABRIC_FREQ_OFFSET;
304 if ((0xB == freq) && (5 == fabric_freq)) {
307 core_avs = reg_read(CORE_AVS_CONTROL_0REG);
308 DEBUG_RD_REG(CORE_AVS_CONTROL_0REG, core_avs);
311 * Set core lower limit = 0.9V &
312 * core upper limit = 0.9125V
316 reg_write(CORE_AVS_CONTROL_0REG, core_avs);
317 DEBUG_WR_REG(CORE_AVS_CONTROL_0REG, core_avs);
319 core_avs = reg_read(CORE_AVS_CONTROL_2REG);
320 DEBUG_RD_REG(CORE_AVS_CONTROL_2REG, core_avs);
321 core_avs |= (1 << 9); /* core AVS enable */
322 reg_write(CORE_AVS_CONTROL_2REG, core_avs);
323 DEBUG_WR_REG(CORE_AVS_CONTROL_2REG, core_avs);
325 tmp2 = reg_read(GENERAL_PURPOSE_RESERVED0_REG);
326 DEBUG_RD_REG(GENERAL_PURPOSE_RESERVED0_REG,
328 tmp2 |= 0x1; /* AvsCoreAvddDetEn enable */
329 reg_write(GENERAL_PURPOSE_RESERVED0_REG, tmp2);
330 DEBUG_WR_REG(GENERAL_PURPOSE_RESERVED0_REG,
334 reg_write(CPU_AVS_CONTROL2_REG, cpu_avs);
335 DEBUG_WR_REG(CPU_AVS_CONTROL2_REG, cpu_avs);
338 info = board_serdes_cfg_get(PEX_MODE_GET(satr11));
339 DEBUG_INIT_FULL_S("info->line0_7= 0x");
340 DEBUG_INIT_FULL_D(info->line0_7, 8);
341 DEBUG_INIT_FULL_S(" info->line8_15= 0x");
342 DEBUG_INIT_FULL_D(info->line8_15, 8);
343 DEBUG_INIT_FULL_S("\n");
346 DEBUG_INIT_S("Hight speed PHY Error #1\n");
350 if (config_module & ETM_MODULE_DETECT) { /* step 0.9 ETM */
351 DEBUG_INIT_FULL_S("ETM module detect Step 0.9:\n");
352 reg_write(SERDES_LINE_MUX_REG_0_7, 0x11111111);
353 DEBUG_WR_REG(SERDES_LINE_MUX_REG_0_7, 0x11111111);
354 info->pex_mode[1] = PEX_BUS_DISABLED; /* pex unit 1 is configure for ETM */
356 reg_write(PEX_PHY_ACCESS_REG(1), (0x002 << 16) | 0xf44d); /* SETM0 - start calibration */
357 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x002 << 16) | 0xf44d); /* SETM0 - start calibration */
358 reg_write(PEX_PHY_ACCESS_REG(1), (0x302 << 16) | 0xf44d); /* SETM1 - start calibration */
359 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x302 << 16) | 0xf44d); /* SETM1 - start calibration */
360 reg_write(PEX_PHY_ACCESS_REG(1), (0x001 << 16) | 0xf801); /* SETM0 - SATA mode & 25MHz ref clk */
361 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x001 << 16) | 0xf801); /* SETM0 - SATA mode & 25MHz ref clk */
362 reg_write(PEX_PHY_ACCESS_REG(1), (0x301 << 16) | 0xf801); /* SETM1 - SATA mode & 25MHz ref clk */
363 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x301 << 16) | 0xf801); /* SETM1 - SATA mode & 25MHz ref clk */
364 reg_write(PEX_PHY_ACCESS_REG(1), (0x011 << 16) | 0x0BFF); /* SETM0 - G3 full swing AMP */
365 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x011 << 16) | 0x0BFF); /* SETM0 - G3 full swing AMP */
366 reg_write(PEX_PHY_ACCESS_REG(1), (0x311 << 16) | 0x0BFF); /* SETM1 - G3 full swing AMP */
367 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x311 << 16) | 0x0BFF); /* SETM1 - G3 full swing AMP */
368 reg_write(PEX_PHY_ACCESS_REG(1), (0x023 << 16) | 0x0800); /* SETM0 - 40 data bit width */
369 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x023 << 16) | 0x0800); /* SETM0 - 40 data bit width */
370 reg_write(PEX_PHY_ACCESS_REG(1), (0x323 << 16) | 0x0800); /* SETM1 - 40 data bit width */
371 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x323 << 16) | 0x0800); /* SETM1 - 40 data bit width */
372 reg_write(PEX_PHY_ACCESS_REG(1), (0x046 << 16) | 0x0400); /* lane0(serdes4) */
373 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x046 << 16) | 0x0400); /* lane0(serdes4) */
374 reg_write(PEX_PHY_ACCESS_REG(1), (0x346 << 16) | 0x0400); /* lane3(serdes7) */
375 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x346 << 16) | 0x0400); /* lane3(serdes7) */
378 /* STEP -1 [PEX-Only] First phase of PEX-PIPE Configuration: */
379 DEBUG_INIT_FULL_S("Step 1: First phase of PEX-PIPE Configuration\n");
380 for (pex_unit = 0; pex_unit < pex_max_unit_get(); pex_unit++) {
381 if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
384 /* 1. GLOB_CLK_CTRL Reset and Clock Control */
385 reg_write(PEX_PHY_ACCESS_REG(pex_unit), (0xC1 << 16) | 0x25);
386 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), (0xC1 << 16) | 0x25);
388 /* 2. GLOB_TEST_CTRL Test Mode Control */
389 if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4) {
390 reg_write(PEX_PHY_ACCESS_REG(pex_unit),
391 (0xC2 << 16) | 0x200);
392 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
393 (0xC2 << 16) | 0x200);
396 /* 3. GLOB_CLK_SRC_LO Clock Source Low */
397 if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X1) {
398 reg_write(PEX_PHY_ACCESS_REG(pex_unit),
399 (0xC3 << 16) | 0x0F);
400 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
401 (0xC3 << 16) | 0x0F);
404 reg_write(PEX_PHY_ACCESS_REG(pex_unit), (0xC5 << 16) | 0x11F);
405 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
406 (0xC5 << 16) | 0x11F);
410 * 2 Configure the desire PIN_PHY_GEN and do power down to the PU_PLL,
411 * PU_RX,PU_TX. (bits[12:5])
413 DEBUG_INIT_FULL_S("Step 2: Configure the desire PIN_PHY_GEN\n");
414 for (line_num = 0; line_num < max_serdes_lines; line_num++) {
415 line_cfg = get_line_cfg(line_num, info);
416 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
418 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX])
420 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SATA]) {
431 ("SATA port error for serdes line: ",
435 tmp = reg_read(SATA_LP_PHY_EXT_CTRL_REG(sata_port));
436 DEBUG_RD_REG(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
437 tmp &= ~((0x1ff << 5) | 0x7);
438 tmp |= ((info->bus_speed & (1 << line_num)) != 0) ?
441 reg_write(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
442 DEBUG_WR_REG(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
445 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
447 * 4) Configure the desire PIN_PHY_GEN and do power
448 * down to the PU_PLL,PU_RX,PU_TX. (bits[12:5])
450 tmp = reg_read(SGMII_SERDES_CFG_REG(0));
451 DEBUG_RD_REG(SGMII_SERDES_CFG_REG(0), tmp);
452 tmp &= ~((0x1ff << 5) | 0x7);
454 reg_write(SGMII_SERDES_CFG_REG(0), tmp);
455 DEBUG_WR_REG(SGMII_SERDES_CFG_REG(0), tmp);
459 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII0])
461 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII1])
463 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII2])
465 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII3])
470 tmp = reg_read(SGMII_SERDES_CFG_REG(sgmii_port));
471 DEBUG_RD_REG(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
472 tmp &= ~((0x1ff << 5) | 0x7);
473 tmp |= (((info->bus_speed & (1 << line_num)) != 0) ?
474 (0x88 << 5) : (0x66 << 5));
475 reg_write(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
476 DEBUG_WR_REG(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
479 /* Step 3 - QSGMII enable */
480 DEBUG_INIT_FULL_S("Step 3 QSGMII enable\n");
481 for (line_num = 0; line_num < max_serdes_lines; line_num++) {
482 line_cfg = get_line_cfg(line_num, info);
483 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
484 /* QSGMII Active bit set to true */
485 tmp = reg_read(QSGMII_CONTROL_1_REG);
486 DEBUG_RD_REG(QSGMII_CONTROL_1_REG, tmp);
488 #ifdef ERRATA_GL_6572255
491 reg_write(QSGMII_CONTROL_1_REG, tmp);
492 DEBUG_WR_REG(QSGMII_CONTROL_1_REG, tmp);
496 /* Step 4 - configure SERDES MUXes */
497 DEBUG_INIT_FULL_S("Step 4: Configure SERDES MUXes\n");
498 if (config_module & ETM_MODULE_DETECT) {
499 reg_write(SERDES_LINE_MUX_REG_0_7, 0x40041111);
500 DEBUG_WR_REG(SERDES_LINE_MUX_REG_0_7, 0x40041111);
502 reg_write(SERDES_LINE_MUX_REG_0_7, info->line0_7);
503 DEBUG_WR_REG(SERDES_LINE_MUX_REG_0_7, info->line0_7);
505 reg_write(SERDES_LINE_MUX_REG_8_15, info->line8_15);
506 DEBUG_WR_REG(SERDES_LINE_MUX_REG_8_15, info->line8_15);
508 /* Step 5: Activate the RX High Impedance Mode */
509 DEBUG_INIT_FULL_S("Step 5: Activate the RX High Impedance Mode\n");
510 rx_high_imp_mode = 0x8080;
511 if (device_rev == 2) /* for B0 only */
512 rx_high_imp_mode |= 4;
514 for (line_num = 0; line_num < max_serdes_lines; line_num++) {
515 /* for each serdes lane */
516 DEBUG_INIT_FULL_S("SERDES ");
517 DEBUG_INIT_FULL_D_10(line_num, 2);
518 line_cfg = get_line_cfg(line_num, info);
519 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED]) {
520 DEBUG_INIT_FULL_S(" unconnected ***\n");
523 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX]) {
524 pex_unit = line_num >> 2;
525 pex_line_num = line_num % 4;
526 DEBUG_INIT_FULL_S(" - PEX unit ");
527 DEBUG_INIT_FULL_D_10(pex_unit, 1);
528 DEBUG_INIT_FULL_S(" line= ");
529 DEBUG_INIT_FULL_D_10(pex_line_num, 1);
530 DEBUG_INIT_FULL_S("\n");
532 /* Needed for PEX_PHY_ACCESS_REG macro */
533 if ((line_num > 7) &&
534 (info->pex_mode[3] == PEX_BUS_MODE_X8))
535 /* lines 8 - 15 are belong to PEX3 in x8 mode */
538 if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
542 * 8) Activate the RX High Impedance Mode field
543 * (bit [2]) in register /PCIe_USB Control (Each MAC
544 * contain different Access to reach its
546 * [PEX-Only] Set bit[12]: The analog part latches idle
547 * if PU_TX = 1 and PU_PLL =1.
550 /* Termination enable */
551 if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X1) {
552 in_direct = (0x48 << 16) | (pex_line_num << 24) |
553 0x1000 | rx_high_imp_mode; /* x1 */
554 } else if ((info->pex_mode[pex_unit] ==
555 PEX_BUS_MODE_X4) && (pex_line_num == 0))
556 in_direct = (0x48 << 16) | (pex_line_num << 24) |
557 0x1000 | (rx_high_imp_mode & 0xff); /* x4 */
562 reg_write(PEX_PHY_ACCESS_REG(pex_unit),
564 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
571 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SATA]) {
573 * port 0 for serdes lines 4,6, and port 1 for
576 sata_port = line_num & 1;
577 DEBUG_INIT_FULL_S(" - SATA port ");
578 DEBUG_INIT_FULL_D_10(sata_port, 2);
579 DEBUG_INIT_FULL_S("\n");
580 reg_write(SATA_COMPHY_CTRL_REG(sata_port),
582 DEBUG_WR_REG(SATA_COMPHY_CTRL_REG(sata_port),
587 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
588 DEBUG_INIT_FULL_S(" - QSGMII\n");
589 reg_write(SGMII_COMPHY_CTRL_REG(0), rx_high_imp_mode);
590 DEBUG_WR_REG(SGMII_COMPHY_CTRL_REG(0),
595 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII0])
597 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII1])
599 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII2])
601 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII3])
605 DEBUG_INIT_FULL_S(" - SGMII port ");
606 DEBUG_INIT_FULL_D_10(sgmii_port, 2);
607 DEBUG_INIT_FULL_S("\n");
608 reg_write(SGMII_COMPHY_CTRL_REG(sgmii_port), rx_high_imp_mode);
609 DEBUG_WR_REG(SGMII_COMPHY_CTRL_REG(sgmii_port),
611 } /* for each serdes lane */
613 /* Step 6 [PEX-Only] PEX-Main configuration (X4 or X1): */
614 DEBUG_INIT_FULL_S("Step 6: [PEX-Only] PEX-Main configuration (X4 or X1)\n");
615 tmp = reg_read(SOC_CTRL_REG);
616 DEBUG_RD_REG(SOC_CTRL_REG, tmp);
618 if (info->pex_mode[0] == PEX_BUS_MODE_X1)
619 tmp |= PCIE0_QUADX1_EN;
620 if (info->pex_mode[1] == PEX_BUS_MODE_X1)
621 tmp |= PCIE1_QUADX1_EN;
622 if (((reg_read(MPP_SAMPLE_AT_RESET(0)) & PEX_CLK_100MHZ_MASK) >>
623 PEX_CLK_100MHZ_OFFSET) == 0x1)
624 tmp |= (PCIE0_CLK_OUT_EN_MASK | PCIE1_CLK_OUT_EN_MASK);
626 reg_write(SOC_CTRL_REG, tmp);
627 DEBUG_WR_REG(SOC_CTRL_REG, tmp);
629 /* 6.2 PCI Express Link Capabilities */
630 DEBUG_INIT_FULL_S("Step 6.2: [PEX-Only] PCI Express Link Capabilities\n");
632 for (line_num = 0; line_num < max_serdes_lines; line_num++) {
633 line_cfg = get_line_cfg(line_num, info);
635 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX]) {
637 * PCI Express Control
642 pex_unit = line_num >> 2;
643 pex_if = MV_SERDES_NUM_TO_PEX_NUM(line_num);
644 if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
647 /* set Common Clock Configuration */
648 tmp = reg_read(PEX_LINK_CTRL_STATUS_REG(pex_if));
649 DEBUG_RD_REG(PEX_LINK_CTRL_STATUS_REG(pex_if), tmp);
651 reg_write(PEX_LINK_CTRL_STATUS_REG(pex_if), tmp);
652 DEBUG_WR_REG(PEX_LINK_CTRL_STATUS_REG(pex_if), tmp);
654 tmp = reg_read(PEX_LINK_CAPABILITIES_REG(pex_if));
655 DEBUG_RD_REG(PEX_LINK_CAPABILITIES_REG(pex_if), tmp);
657 if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X1)
659 if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4)
661 if (0 == PEX_CAPABILITY_GET(satr11))
665 DEBUG_INIT_FULL_S("Step 6.2: PEX ");
666 DEBUG_INIT_FULL_D(pex_if, 1);
667 DEBUG_INIT_FULL_C(" set GEN", (tmp & 3), 1);
668 reg_write(PEX_LINK_CAPABILITIES_REG(pex_if), tmp);
669 DEBUG_WR_REG(PEX_LINK_CAPABILITIES_REG(pex_if), tmp);
672 * If pex is X4, no need to pass thru the other
675 if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4)
681 * Step 7 [PEX-X4 Only] To create PEX-Link that contain 4-lanes you
682 * need to config the register SOC_Misc/General Purpose2
685 DEBUG_INIT_FULL_S("Step 7: [PEX-X4 Only] To create PEX-Link\n");
686 tmp = reg_read(GEN_PURP_RES_2_REG);
687 DEBUG_RD_REG(GEN_PURP_RES_2_REG, tmp);
690 if (info->pex_mode[0] == PEX_BUS_MODE_X4)
693 if (info->pex_mode[1] == PEX_BUS_MODE_X4)
696 if (info->pex_mode[2] == PEX_BUS_MODE_X4)
699 if (info->pex_mode[3] == PEX_BUS_MODE_X4)
702 reg_write(GEN_PURP_RES_2_REG, tmp);
703 DEBUG_WR_REG(GEN_PURP_RES_2_REG, tmp);
705 /* Steps 8 , 9 ,10 - use prepared REG addresses and values */
706 DEBUG_INIT_FULL_S("Steps 7,8,9,10 and 11\n");
708 /* Prepare PHY parameters for each step according to MUX selection */
709 for (line_num = 0; line_num < max_serdes_lines; line_num++) {
710 /* for each serdes lane */
712 line_cfg = get_line_cfg(line_num, info);
714 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
717 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX]) {
718 pex_unit = line_num >> 2;
719 pex_line_num = line_num % 4;
721 if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
724 * 8) Configure the desire PHY_MODE (bits [7:5])
725 * and REF_FREF_SEL (bits[4:0]) in the register Power
726 * and PLL Control (Each MAC contain different Access
727 * to reach its Serdes-Regfile).
729 if (((info->pex_mode[pex_unit] == PEX_BUS_MODE_X4) &&
731 || ((info->pex_mode[pex_unit] == PEX_BUS_MODE_X1))) {
732 reg_write(PEX_PHY_ACCESS_REG(pex_unit),
733 (0x01 << 16) | (pex_line_num << 24) |
735 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
736 (0x01 << 16) | (pex_line_num << 24)
739 * Step 8.1: [PEX-Only] Configure Max PLL Rate
740 * (bit 8 in KVCO Calibration Control and
743 /* Use Maximum PLL Rate(Bit 8) */
744 reg_write(PEX_PHY_ACCESS_REG(pex_unit),
745 (0x02 << 16) | (1 << 31) |
746 (pex_line_num << 24)); /* read command */
747 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
748 (0x02 << 16) | (1 << 31) |
749 (pex_line_num << 24));
750 tmp = reg_read(PEX_PHY_ACCESS_REG(pex_unit));
751 DEBUG_RD_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp);
754 reg_write(PEX_PHY_ACCESS_REG(pex_unit), tmp);
755 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp);
757 /* Use Maximum PLL Rate(Bits [10:9]) */
758 reg_write(PEX_PHY_ACCESS_REG(pex_unit),
759 (0x81 << 16) | (1 << 31) |
760 (pex_line_num << 24)); /* read command */
761 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
762 (0x81 << 16) | (1 << 31) |
763 (pex_line_num << 24));
764 tmp = reg_read(PEX_PHY_ACCESS_REG(pex_unit));
765 DEBUG_RD_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp);
768 reg_write(PEX_PHY_ACCESS_REG(pex_unit), tmp);
769 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp);
775 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SATA]) {
777 * Port 0 for serdes lines 4,6, and port 1 for serdes
780 sata_port = line_num & 1;
783 * 8) Configure the desire PHY_MODE (bits [7:5]) and
784 * REF_FREF_SEL (bits[4:0]) in the register Power
785 * and PLL Control (Each MAC contain different Access
786 * to reach its Serdes-Regfile).
788 reg_write(SATA_PWR_PLL_CTRL_REG(sata_port), 0xF801);
789 DEBUG_WR_REG(SATA_PWR_PLL_CTRL_REG(sata_port), 0xF801);
791 /* 9) Configure the desire SEL_BITS */
792 reg_write(SATA_DIG_LP_ENA_REG(sata_port), 0x400);
793 DEBUG_WR_REG(SATA_DIG_LP_ENA_REG(sata_port), 0x400);
795 /* 10) Configure the desire REFCLK_SEL */
797 reg_write(SATA_REF_CLK_SEL_REG(sata_port), 0x400);
798 DEBUG_WR_REG(SATA_REF_CLK_SEL_REG(sata_port), 0x400);
800 /* 11) Power up to the PU_PLL,PU_RX,PU_TX. */
801 tmp = reg_read(SATA_LP_PHY_EXT_CTRL_REG(sata_port));
802 DEBUG_RD_REG(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
804 reg_write(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
805 DEBUG_WR_REG(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
810 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
812 * 8) Configure the desire PHY_MODE (bits [7:5])
813 * and REF_FREF_SEL (bits[4:0]) in the register
815 reg_write(SGMII_PWR_PLL_CTRL_REG(0), 0xF881);
816 DEBUG_WR_REG(SGMII_PWR_PLL_CTRL_REG(0), 0xF881);
819 * 9) Configure the desire SEL_BITS (bits [11:0]
822 reg_write(SGMII_DIG_LP_ENA_REG(0), 0x400);
823 DEBUG_WR_REG(SGMII_DIG_LP_ENA_REG(0), 0x400);
826 * 10) Configure the desire REFCLK_SEL (bit [10])
829 reg_write(SGMII_REF_CLK_SEL_REG(0), 0x400);
830 DEBUG_WR_REG(SGMII_REF_CLK_SEL_REG(0), 0x400);
832 /* 11) Power up to the PU_PLL,PU_RX,PU_TX. */
833 tmp = reg_read(SGMII_SERDES_CFG_REG(0));
834 DEBUG_RD_REG(SGMII_SERDES_CFG_REG(0), tmp);
836 reg_write(SGMII_SERDES_CFG_REG(0), tmp);
837 DEBUG_WR_REG(SGMII_SERDES_CFG_REG(0), tmp);
841 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII0])
843 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII1])
845 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII2])
847 else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII3])
853 * 8) Configure the desire PHY_MODE (bits [7:5]) and
854 * REF_FREF_SEL (bits[4:0]) in the register
856 reg_write(SGMII_PWR_PLL_CTRL_REG(sgmii_port), 0xF881);
857 DEBUG_WR_REG(SGMII_PWR_PLL_CTRL_REG(sgmii_port), 0xF881);
859 /* 9) Configure the desire SEL_BITS (bits [11:0] in register */
860 reg_write(SGMII_DIG_LP_ENA_REG(sgmii_port), 0);
861 DEBUG_WR_REG(SGMII_DIG_LP_ENA_REG(sgmii_port), 0);
863 /* 10) Configure the desire REFCLK_SEL (bit [10]) in register */
864 reg_write(SGMII_REF_CLK_SEL_REG(sgmii_port), 0x400);
865 DEBUG_WR_REG(SGMII_REF_CLK_SEL_REG(sgmii_port), 0x400);
867 /* 11) Power up to the PU_PLL,PU_RX,PU_TX. */
868 tmp = reg_read(SGMII_SERDES_CFG_REG(sgmii_port));
869 DEBUG_RD_REG(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
871 reg_write(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
872 DEBUG_WR_REG(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
874 } /* for each serdes lane */
876 /* Step 12 [PEX-Only] Last phase of PEX-PIPE Configuration */
877 DEBUG_INIT_FULL_S("Steps 12: [PEX-Only] Last phase of PEX-PIPE Configuration\n");
878 for (line_num = 0; line_num < max_serdes_lines; line_num++) {
879 /* for each serdes lane */
881 line_cfg = get_line_cfg(line_num, info);
883 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
886 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX]) {
887 pex_unit = line_num >> 2;
888 pex_line_num = line_num % 4;
889 if (0 == pex_line_num) {
890 reg_write(PEX_PHY_ACCESS_REG(pex_unit),
891 (0xC1 << 16) | 0x24);
892 DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
893 (0xC1 << 16) | 0x24);
898 /*--------------------------------------------------------------*/
899 /* Step 13: Wait 15ms before checking results */
900 DEBUG_INIT_FULL_S("Steps 13: Wait 15ms before checking results");
905 for (line_num = 0; line_num < max_serdes_lines; line_num++) {
907 line_cfg = get_line_cfg(line_num, info);
909 serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
912 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX])
915 if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SATA]) {
917 * Port 0 for serdes lines 4,6, and port 1
920 sata_port = line_num & 1;
923 reg_read(SATA_LP_PHY_EXT_STAT_REG
925 DEBUG_RD_REG(SATA_LP_PHY_EXT_STAT_REG
927 if ((tmp & 0x7) != 0x7)
933 serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
934 tmp = reg_read(SGMII_SERDES_STAT_REG(0));
935 DEBUG_RD_REG(SGMII_SERDES_STAT_REG(0), tmp);
936 if ((tmp & 0x7) != 0x7)
942 serdes_cfg[line_num][SERDES_UNIT_SGMII0])
945 serdes_cfg[line_num][SERDES_UNIT_SGMII1])
948 serdes_cfg[line_num][SERDES_UNIT_SGMII2])
951 serdes_cfg[line_num][SERDES_UNIT_SGMII3])
956 tmp = reg_read(SGMII_SERDES_STAT_REG(sgmii_port));
957 DEBUG_RD_REG(SGMII_SERDES_STAT_REG(sgmii_port), tmp);
958 if ((tmp & 0x7) != 0x7)
969 * Step14 [PEX-Only] In order to configure RC/EP mode please write
970 * to register 0x0060 bits
972 DEBUG_INIT_FULL_S("Steps 14: [PEX-Only] In order to configure\n");
973 for (pex_unit = 0; pex_unit < pex_max_unit_get(); pex_unit++) {
974 if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
977 reg_read(PEX_CAPABILITIES_REG(MV_PEX_UNIT_TO_IF(pex_unit)));
978 DEBUG_RD_REG(PEX_CAPABILITIES_REG(MV_PEX_UNIT_TO_IF(pex_unit)),
981 if (info->pex_type == MV_PEX_ROOT_COMPLEX)
985 reg_write(PEX_CAPABILITIES_REG(MV_PEX_UNIT_TO_IF(pex_unit)),
987 DEBUG_WR_REG(PEX_CAPABILITIES_REG(MV_PEX_UNIT_TO_IF(pex_unit)),
992 * Step 15 [PEX-Only] Only for EP mode set to Zero bits 19 and 16 of
995 DEBUG_INIT_FULL_S("Steps 15: [PEX-Only] In order to configure\n");
996 for (pex_unit = 0; pex_unit < pex_max_unit_get(); pex_unit++) {
997 if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
999 if (info->pex_type == MV_PEX_END_POINT) {
1001 reg_read(PEX_DBG_CTRL_REG
1002 (MV_PEX_UNIT_TO_IF(pex_unit)));
1003 DEBUG_RD_REG(PEX_DBG_CTRL_REG
1004 (MV_PEX_UNIT_TO_IF(pex_unit)), tmp);
1006 reg_write(PEX_DBG_CTRL_REG(MV_PEX_UNIT_TO_IF(pex_unit)),
1008 DEBUG_WR_REG(PEX_DBG_CTRL_REG
1009 (MV_PEX_UNIT_TO_IF(pex_unit)), tmp);
1013 if (info->serdes_m_phy_change) {
1014 MV_SERDES_CHANGE_M_PHY *serdes_m_phy_change;
1016 for (line_num = 0; line_num < max_serdes_lines; line_num++) {
1017 line_cfg = get_line_cfg(line_num, info);
1019 serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
1021 serdes_m_phy_change = info->serdes_m_phy_change;
1022 bus_speed = info->bus_speed & (1 << line_num);
1023 while (serdes_m_phy_change->type !=
1024 SERDES_UNIT_UNCONNECTED) {
1025 switch (serdes_m_phy_change->type) {
1026 case SERDES_UNIT_PEX:
1027 if (line_cfg != SERDES_UNIT_PEX)
1029 pex_unit = line_num >> 2;
1030 pex_line_num = line_num % 4;
1031 if (info->pex_mode[pex_unit] ==
1034 if ((info->pex_mode[pex_unit] ==
1035 PEX_BUS_MODE_X4) && pex_line_num)
1039 reg_write(PEX_PHY_ACCESS_REG
1041 (pex_line_num << 24) |
1042 serdes_m_phy_change->val_hi_speed);
1043 DEBUG_WR_REG(PEX_PHY_ACCESS_REG
1047 serdes_m_phy_change->val_hi_speed);
1049 reg_write(PEX_PHY_ACCESS_REG
1051 (pex_line_num << 24) |
1052 serdes_m_phy_change->val_low_speed);
1053 DEBUG_WR_REG(PEX_PHY_ACCESS_REG
1057 serdes_m_phy_change->val_low_speed);
1060 case SERDES_UNIT_SATA:
1061 if (line_cfg != SERDES_UNIT_SATA)
1064 * Port 0 for serdes lines 4,6, and
1065 * port 1 for serdes lines 5
1067 sata_port = line_num & 1;
1069 reg_write(SATA_BASE_REG
1071 serdes_m_phy_change->reg_hi_speed,
1072 serdes_m_phy_change->val_hi_speed);
1073 DEBUG_WR_REG(SATA_BASE_REG
1075 serdes_m_phy_change->reg_hi_speed,
1076 serdes_m_phy_change->val_hi_speed);
1078 reg_write(SATA_BASE_REG
1080 serdes_m_phy_change->reg_low_speed,
1081 serdes_m_phy_change->val_low_speed);
1082 DEBUG_WR_REG(SATA_BASE_REG
1084 serdes_m_phy_change->reg_low_speed,
1085 serdes_m_phy_change->val_low_speed);
1088 case SERDES_UNIT_SGMII0:
1089 case SERDES_UNIT_SGMII1:
1090 case SERDES_UNIT_SGMII2:
1091 case SERDES_UNIT_SGMII3:
1092 if (line_cfg == serdes_cfg[line_num]
1093 [SERDES_UNIT_SGMII0])
1095 else if (line_cfg ==
1096 serdes_cfg[line_num]
1097 [SERDES_UNIT_SGMII1])
1099 else if (line_cfg ==
1100 serdes_cfg[line_num]
1101 [SERDES_UNIT_SGMII2])
1103 else if (line_cfg ==
1104 serdes_cfg[line_num]
1105 [SERDES_UNIT_SGMII3])
1110 reg_write(MV_ETH_REGS_BASE
1112 serdes_m_phy_change->reg_hi_speed,
1113 serdes_m_phy_change->val_hi_speed);
1114 DEBUG_WR_REG(MV_ETH_REGS_BASE
1116 serdes_m_phy_change->reg_hi_speed,
1117 serdes_m_phy_change->val_hi_speed);
1119 reg_write(MV_ETH_REGS_BASE
1121 serdes_m_phy_change->reg_low_speed,
1122 serdes_m_phy_change->val_low_speed);
1123 DEBUG_WR_REG(MV_ETH_REGS_BASE
1125 serdes_m_phy_change->reg_low_speed,
1126 serdes_m_phy_change->val_low_speed);
1129 case SERDES_UNIT_QSGMII:
1130 if (line_cfg != SERDES_UNIT_QSGMII)
1134 (serdes_m_phy_change->reg_hi_speed,
1135 serdes_m_phy_change->val_hi_speed);
1137 (serdes_m_phy_change->reg_hi_speed,
1138 serdes_m_phy_change->val_hi_speed);
1141 (serdes_m_phy_change->reg_low_speed,
1142 serdes_m_phy_change->val_low_speed);
1144 (serdes_m_phy_change->reg_low_speed,
1145 serdes_m_phy_change->val_low_speed);
1151 serdes_m_phy_change++;
1156 /* Step 16 [PEX-Only] Training Enable */
1157 DEBUG_INIT_FULL_S("Steps 16: [PEX-Only] Training Enable");
1158 tmp = reg_read(SOC_CTRL_REG);
1159 DEBUG_RD_REG(SOC_CTRL_REG, tmp);
1161 for (pex_unit = 0; pex_unit < pex_max_unit_get(); pex_unit++) {
1162 reg_write(PEX_CAUSE_REG(pex_unit), 0);
1163 DEBUG_WR_REG(PEX_CAUSE_REG(pex_unit), 0);
1164 if (info->pex_mode[pex_unit] != PEX_BUS_DISABLED)
1165 tmp |= (0x1 << pex_unit);
1167 reg_write(SOC_CTRL_REG, tmp);
1168 DEBUG_WR_REG(SOC_CTRL_REG, tmp);
1170 /* Step 17: Speed change to target speed and width */
1172 u32 tmp_reg, tmp_pex_reg;
1174 u32 first_busno, next_busno;
1175 u32 max_link_width = 0;
1176 u32 neg_link_width = 0;
1177 pex_if_num = pex_max_if_get();
1179 DEBUG_INIT_FULL_C("step 17: max_if= 0x", pex_if_num, 1);
1181 for (pex_if = 0; pex_if < pex_if_num; pex_if++) {
1182 line_num = (pex_if <= 8) ? pex_if : 12;
1183 line_cfg = get_line_cfg(line_num, info);
1184 if (line_cfg != serdes_cfg[line_num][SERDES_UNIT_PEX])
1186 pex_unit = (pex_if < 9) ? (pex_if >> 2) : 3;
1187 DEBUG_INIT_FULL_S("step 17: PEX");
1188 DEBUG_INIT_FULL_D(pex_if, 1);
1189 DEBUG_INIT_FULL_C(" pex_unit= ", pex_unit, 1);
1191 if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED) {
1192 DEBUG_INIT_FULL_C("PEX disabled interface ",
1198 first_busno = next_busno;
1199 if ((info->pex_type == MV_PEX_END_POINT) &&
1201 if ((pex_if < 8) && (info->pex_mode[pex_unit] ==
1207 tmp = reg_read(PEX_DBG_STATUS_REG(pex_if));
1208 DEBUG_RD_REG(PEX_DBG_STATUS_REG(pex_if), tmp);
1209 if ((tmp & 0x7f) == 0x7e) {
1211 tmp = reg_read(PEX_LINK_CAPABILITIES_REG(pex_if));
1212 max_link_width = tmp;
1213 DEBUG_RD_REG((PEX_LINK_CAPABILITIES_REG
1215 max_link_width = ((max_link_width >> 4) & 0x3F);
1217 reg_read(PEX_LINK_CTRL_STATUS_REG(pex_if));
1218 DEBUG_RD_REG((PEX_LINK_CTRL_STATUS_REG(pex_if)),
1220 neg_link_width = ((neg_link_width >> 20) & 0x3F);
1221 if (max_link_width > neg_link_width) {
1222 tmp &= ~(0x3F << 4);
1223 tmp |= (neg_link_width << 4);
1224 reg_write(PEX_LINK_CAPABILITIES_REG
1226 DEBUG_WR_REG((PEX_LINK_CAPABILITIES_REG
1228 mdelay(1); /* wait 1ms before reading capability for speed */
1229 DEBUG_INIT_S("PEX");
1230 DEBUG_INIT_D(pex_if, 1);
1231 DEBUG_INIT_C(": change width to X",
1235 reg_read((PEX_CFG_DIRECT_ACCESS
1237 PEX_LINK_CAPABILITY_REG)));
1238 DEBUG_RD_REG((PEX_CFG_DIRECT_ACCESS
1240 PEX_LINK_CAPABILITY_REG)),
1242 tmp_pex_reg &= (0xF);
1243 if (tmp_pex_reg == 0x2) {
1246 (PEX_CFG_DIRECT_ACCESS
1248 PEX_LINK_CTRL_STAT_REG)) &
1250 DEBUG_RD_REG(PEX_CFG_DIRECT_ACCESS
1252 PEX_LINK_CTRL_STAT_REG),
1254 /* check if the link established is GEN1 */
1255 if (tmp_reg == 0x1) {
1256 pex_local_bus_num_set(pex_if,
1258 pex_local_dev_num_set(pex_if,
1261 DEBUG_INIT_FULL_S("** Link is Gen1, check the EP capability\n");
1262 /* link is Gen1, check the EP capability */
1264 pex_cfg_read(pex_if,
1268 DEBUG_INIT_FULL_C("pex_cfg_read: return addr=0x%x",
1271 DEBUG_INIT_FULL_C("pex_cfg_read: return 0xff -->PEX (%d): Detected No Link.",
1275 while ((pex_cfg_read
1276 (pex_if, first_busno, 0,
1288 (pex_if, first_busno, 0, 0,
1289 addr + 0xC) & 0xF) >=
1293 (PEX_LINK_CTRL_STATUS2_REG
1296 (PEX_LINK_CTRL_STATUS2_REG
1298 tmp &= ~(0x1 | 1 << 1);
1301 (PEX_LINK_CTRL_STATUS2_REG
1304 (PEX_LINK_CTRL_STATUS2_REG
1315 reg_write(PEX_CTRL_REG
1321 mdelay(10); /* We need to wait 10ms before reading the PEX_DBG_STATUS_REG in order not to read the status of the former state */
1331 DEBUG_INIT_FULL_S("PEX");
1332 DEBUG_INIT_FULL_D(pex_if, 1);
1333 DEBUG_INIT_FULL_S(" : Detected No Link. Status Reg(0x");
1334 DEBUG_INIT_FULL_D(PEX_DBG_STATUS_REG(pex_if),
1336 DEBUG_INIT_FULL_C(") = 0x", tmp, 8);
1340 (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4))
1345 /* Step 18: update pex DEVICE ID */
1348 pex_if_num = pex_max_if_get();
1349 ctrl_mode = ctrl_model_get();
1350 for (pex_if = 0; pex_if < pex_if_num; pex_if++) {
1351 pex_unit = (pex_if < 9) ? (pex_if >> 2) : 3;
1352 if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED) {
1354 (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4))
1359 devId = reg_read(PEX_CFG_DIRECT_ACCESS(
1360 pex_if, PEX_DEVICE_AND_VENDOR_ID));
1362 devId |= ((ctrl_mode << 16) & 0xffff0000);
1363 DEBUG_INIT_FULL_S("Update Device ID PEX");
1364 DEBUG_INIT_FULL_D(pex_if, 1);
1365 DEBUG_INIT_FULL_D(devId, 8);
1366 DEBUG_INIT_FULL_S("\n");
1367 reg_write(PEX_CFG_DIRECT_ACCESS
1368 (pex_if, PEX_DEVICE_AND_VENDOR_ID), devId);
1370 (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4))
1373 DEBUG_INIT_FULL_S("Update PEX Device ID 0x");
1374 DEBUG_INIT_FULL_D(ctrl_mode, 4);
1375 DEBUG_INIT_FULL_S("0\n");
1377 tmp = reg_read(PEX_DBG_STATUS_REG(0));
1378 DEBUG_RD_REG(PEX_DBG_STATUS_REG(0), tmp);
1380 DEBUG_INIT_S(ENDED_OK);
1384 /* PEX configuration space read write */
1387 * pex_cfg_read - Read from configuration space
1390 * This function performs a 32 bit read from PEX configuration space.
1391 * It supports both type 0 and type 1 of Configuration Transactions
1392 * (local and over bridge). In order to read from local bus segment, use
1393 * bus number retrieved from mvPexLocalBusNumGet(). Other bus numbers
1394 * will result configuration transaction of type 1 (over bridge).
1397 * pex_if - PEX interface number.
1398 * bus - PEX segment bus number.
1399 * dev - PEX device number.
1400 * func - Function number.
1401 * offss - Register offset.
1407 * 32bit register data, 0xffffffff on error
1410 u32 pex_cfg_read(u32 pex_if, u32 bus, u32 dev, u32 func, u32 offs)
1413 u32 local_dev, local_bus;
1416 if (pex_if >= MV_PEX_MAX_IF)
1419 if (dev >= MAX_PEX_DEVICES) {
1420 DEBUG_INIT_C("pex_cfg_read: ERR. device number illigal ", dev,
1425 if (func >= MAX_PEX_FUNCS) {
1426 DEBUG_INIT_C("pex_cfg_read: ERR. function num illigal ", func,
1431 if (bus >= MAX_PEX_BUSSES) {
1432 DEBUG_INIT_C("pex_cfg_read: ERR. bus number illigal ", bus, 1);
1435 val = reg_read(PEX_STATUS_REG(pex_if));
1438 ((val & PXSR_PEX_DEV_NUM_MASK) >> PXSR_PEX_DEV_NUM_OFFS);
1440 ((val & PXSR_PEX_BUS_NUM_MASK) >> PXSR_PEX_BUS_NUM_OFFS);
1442 /* Speed up the process. In case on no link, return MV_ERROR */
1443 if ((dev != local_dev) || (bus != local_bus)) {
1444 pex_data = reg_read(PEX_STATUS_REG(pex_if));
1446 if ((pex_data & PXSR_DL_DOWN))
1451 * In PCI Express we have only one device number
1452 * and this number is the first number we encounter else that the
1453 * local_dev spec pex define return on config read/write on any device
1455 if (bus == local_bus) {
1456 if (local_dev == 0) {
1458 * If local dev is 0 then the first number we encounter
1461 if ((dev != 1) && (dev != local_dev))
1465 * If local dev is not 0 then the first number we
1468 if ((dev != 0) && (dev != local_dev))
1473 /* Creating PEX address to be passed */
1474 pex_data = (bus << PXCAR_BUS_NUM_OFFS);
1475 pex_data |= (dev << PXCAR_DEVICE_NUM_OFFS);
1476 pex_data |= (func << PXCAR_FUNC_NUM_OFFS);
1477 pex_data |= (offs & PXCAR_REG_NUM_MASK); /* lgacy register space */
1478 /* extended register space */
1479 pex_data |= (((offs & PXCAR_REAL_EXT_REG_NUM_MASK) >>
1480 PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS);
1482 pex_data |= PXCAR_CONFIG_EN;
1484 /* Write the address to the PEX configuration address register */
1485 reg_write(PEX_CFG_ADDR_REG(pex_if), pex_data);
1488 * In order to let the PEX controller absorbed the address of the read
1489 * transaction we perform a validity check that the address was written
1491 if (pex_data != reg_read(PEX_CFG_ADDR_REG(pex_if)))
1494 /* cleaning Master Abort */
1495 reg_bit_set(PEX_CFG_DIRECT_ACCESS(pex_if, PEX_STATUS_AND_COMMAND),
1497 /* Read the Data returned in the PEX Data register */
1498 pex_data = reg_read(PEX_CFG_DATA_REG(pex_if));
1500 DEBUG_INIT_FULL_C(" --> ", pex_data, 4);
1506 * pex_local_bus_num_set - Set PEX interface local bus number.
1509 * This function sets given PEX interface its local bus number.
1510 * Note: In case the PEX interface is PEX-X, the information is read-only.
1513 * pex_if - PEX interface number.
1514 * bus_num - Bus number.
1520 * MV_NOT_ALLOWED in case PEX interface is PEX-X.
1521 * MV_BAD_PARAM on bad parameters ,
1525 int pex_local_bus_num_set(u32 pex_if, u32 bus_num)
1529 if (bus_num >= MAX_PEX_BUSSES) {
1530 DEBUG_INIT_C("pex_local_bus_num_set: ERR. bus number illigal %d\n",
1535 val = reg_read(PEX_STATUS_REG(pex_if));
1536 val &= ~PXSR_PEX_BUS_NUM_MASK;
1537 val |= (bus_num << PXSR_PEX_BUS_NUM_OFFS) & PXSR_PEX_BUS_NUM_MASK;
1538 reg_write(PEX_STATUS_REG(pex_if), val);
1544 * pex_local_dev_num_set - Set PEX interface local device number.
1547 * This function sets given PEX interface its local device number.
1548 * Note: In case the PEX interface is PEX-X, the information is read-only.
1551 * pex_if - PEX interface number.
1552 * dev_num - Device number.
1558 * MV_NOT_ALLOWED in case PEX interface is PEX-X.
1559 * MV_BAD_PARAM on bad parameters ,
1563 int pex_local_dev_num_set(u32 pex_if, u32 dev_num)
1567 if (pex_if >= MV_PEX_MAX_IF)
1568 return MV_BAD_PARAM;
1570 val = reg_read(PEX_STATUS_REG(pex_if));
1571 val &= ~PXSR_PEX_DEV_NUM_MASK;
1572 val |= (dev_num << PXSR_PEX_DEV_NUM_OFFS) & PXSR_PEX_DEV_NUM_MASK;
1573 reg_write(PEX_STATUS_REG(pex_if), val);