4 bool "Support Rockchip RK3036"
9 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
10 including NEON and GPU, Mali-400 graphics, several DDR3 options
11 and video codec support. Peripherals include Gigabit Ethernet,
12 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
14 config ROCKCHIP_RK3128
15 bool "Support Rockchip RK3128"
18 The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
19 including NEON and GPU, Mali-400 graphics, several DDR3 options
20 and video codec support. Peripherals include Gigabit Ethernet,
21 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
23 config ROCKCHIP_RK3188
24 bool "Support Rockchip RK3188"
26 select SPL_BOARD_INIT if SPL
34 select SPL_DRIVERS_MISC_SUPPORT
35 select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
36 select BOARD_LATE_INIT
37 select ROCKCHIP_BROM_HELPER
39 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
40 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
41 video interfaces, several memory options and video codec support.
42 Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
43 UART, SPI, I2C and PWMs.
45 config ROCKCHIP_RK322X
46 bool "Support Rockchip RK3228/RK3229"
50 select ROCKCHIP_BROM_HELPER
51 select DEBUG_UART_BOARD_INIT
53 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
54 including NEON and GPU, Mali-400 graphics, several DDR3 options
55 and video codec support. Peripherals include Gigabit Ethernet,
56 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
58 config ROCKCHIP_RK3288
59 bool "Support Rockchip RK3288"
61 select SPL_BOARD_INIT if SPL
65 The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
66 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
67 video interfaces supporting HDMI and eDP, several DDR3 options
68 and video codec support. Peripherals include Gigabit Ethernet,
69 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
71 config ROCKCHIP_RK3328
72 bool "Support Rockchip RK3328"
75 The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
76 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
77 video interfaces supporting HDMI and eDP, several DDR3 options
78 and video codec support. Peripherals include Gigabit Ethernet,
79 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
81 config ROCKCHIP_RK3368
82 bool "Support Rockchip RK3368"
86 select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
87 select TPL_NEEDS_SEPARATE_STACK if TPL
88 imply SPL_SEPARATE_BSS
89 imply SPL_SERIAL_SUPPORT
90 imply TPL_SERIAL_SUPPORT
91 select DEBUG_UART_BOARD_INIT
94 The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
95 into a big and little cluster with 4 cores each) Cortex-A53 including
96 AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache
97 (for the little cluster), PowerVR G6110 based graphics, one video
98 output processor supporting LVDS/HDMI/eDP, several DDR3 options and
101 On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO,
102 I2S, UARTs, SPI, I2C and PWMs.
107 default "arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds"
120 config ROCKCHIP_RK3399
121 bool "Support Rockchip RK3399"
125 select SPL_SEPARATE_BSS
126 select SPL_SERIAL_SUPPORT
127 select SPL_DRIVERS_MISC_SUPPORT
128 select DEBUG_UART_BOARD_INIT
129 select BOARD_LATE_INIT
130 select ROCKCHIP_BROM_HELPER
132 The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
133 and quad-core Cortex-A53.
134 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
135 video interfaces supporting HDMI and eDP, several DDR3 options
136 and video codec support. Peripherals include Gigabit Ethernet,
137 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
139 config ROCKCHIP_RV1108
140 bool "Support Rockchip RV1108"
143 The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
146 config SPL_ROCKCHIP_BACK_TO_BROM
147 bool "SPL returns to bootrom"
148 default y if ROCKCHIP_RK3036
149 select ROCKCHIP_BROM_HELPER
152 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
153 SPL will return to the boot rom, which will then load the U-Boot
154 binary to keep going on.
156 config TPL_ROCKCHIP_BACK_TO_BROM
157 bool "TPL returns to bootrom"
158 default y if ROCKCHIP_RK3368
159 select ROCKCHIP_BROM_HELPER
162 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
163 SPL will return to the boot rom, which will then load the U-Boot
164 binary to keep going on.
166 config ROCKCHIP_BOOT_MODE_REG
167 hex "Rockchip boot mode flag register address"
168 default 0x200081c8 if ROCKCHIP_RK3036
169 default 0x20004040 if ROCKCHIP_RK3188
170 default 0x110005c8 if ROCKCHIP_RK322X
171 default 0xff730094 if ROCKCHIP_RK3288
172 default 0xff738200 if ROCKCHIP_RK3368
173 default 0xff320300 if ROCKCHIP_RK3399
174 default 0x10300580 if ROCKCHIP_RV1108
177 The Soc will enter to different boot mode(defined in asm/arch/boot_mode.h)
178 according to the value from this register.
180 config ROCKCHIP_SPL_RESERVE_IRAM
181 hex "Size of IRAM reserved in SPL"
184 SPL may need reserve memory for firmware loaded by SPL, whose load
185 address is in IRAM and may overlay with SPL text area if not
188 config ROCKCHIP_BROM_HELPER
191 config SPL_ROCKCHIP_EARLYRETURN_TO_BROM
192 bool "SPL requires early-return (for RK3188-style BROM) to BROM"
193 depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK
195 Some Rockchip BROM variants (e.g. on the RK3188) load the
196 first stage in segments and enter multiple times. E.g. on
197 the RK3188, the first 1KB of the first stage are loaded
198 first and entered; after returning to the BROM, the
199 remainder of the first stage is loaded, but the BROM
200 re-enters at the same address/to the same code as previously.
202 This enables support code in the BOOT0 hook for the SPL stage
203 to allow multiple entries.
205 config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
206 bool "TPL requires early-return (for RK3188-style BROM) to BROM"
207 depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK
209 Some Rockchip BROM variants (e.g. on the RK3188) load the
210 first stage in segments and enter multiple times. E.g. on
211 the RK3188, the first 1KB of the first stage are loaded
212 first and entered; after returning to the BROM, the
213 remainder of the first stage is loaded, but the BROM
214 re-enters at the same address/to the same code as previously.
216 This enables support code in the BOOT0 hook for the TPL stage
217 to allow multiple entries.
219 config SPL_MMC_SUPPORT
220 default y if !SPL_ROCKCHIP_BACK_TO_BROM
222 source "arch/arm/mach-rockchip/rk3036/Kconfig"
223 source "arch/arm/mach-rockchip/rk3128/Kconfig"
224 source "arch/arm/mach-rockchip/rk3188/Kconfig"
225 source "arch/arm/mach-rockchip/rk322x/Kconfig"
226 source "arch/arm/mach-rockchip/rk3288/Kconfig"
227 source "arch/arm/mach-rockchip/rk3328/Kconfig"
228 source "arch/arm/mach-rockchip/rk3368/Kconfig"
229 source "arch/arm/mach-rockchip/rk3399/Kconfig"
230 source "arch/arm/mach-rockchip/rv1108/Kconfig"