3 config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
6 config TARGET_SOCFPGA_ARRIA5
8 select TARGET_SOCFPGA_GEN5
10 config TARGET_SOCFPGA_ARRIA10
12 select SPL_BOARD_INIT if SPL
15 config TARGET_SOCFPGA_CYCLONE5
17 select TARGET_SOCFPGA_GEN5
19 config TARGET_SOCFPGA_GEN5
24 prompt "Altera SOCFPGA board select"
27 config TARGET_SOCFPGA_ARRIA10_SOCDK
28 bool "Altera SOCFPGA SoCDK (Arria 10)"
29 select TARGET_SOCFPGA_ARRIA10
31 config TARGET_SOCFPGA_ARRIA5_SOCDK
32 bool "Altera SOCFPGA SoCDK (Arria V)"
33 select TARGET_SOCFPGA_ARRIA5
35 config TARGET_SOCFPGA_CYCLONE5_SOCDK
36 bool "Altera SOCFPGA SoCDK (Cyclone V)"
37 select TARGET_SOCFPGA_CYCLONE5
39 config TARGET_SOCFPGA_ARIES_MCVEVK
40 bool "Aries MCVEVK (Cyclone V)"
41 select TARGET_SOCFPGA_CYCLONE5
43 config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
44 bool "Devboards DBM-SoC1 (Cyclone V)"
45 select TARGET_SOCFPGA_CYCLONE5
47 config TARGET_SOCFPGA_EBV_SOCRATES
48 bool "EBV SoCrates (Cyclone V)"
49 select TARGET_SOCFPGA_CYCLONE5
51 config TARGET_SOCFPGA_IS1
52 bool "IS1 (Cyclone V)"
53 select TARGET_SOCFPGA_CYCLONE5
55 config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
56 bool "samtec VIN|ING FPGA (Cyclone V)"
57 select BOARD_LATE_INIT
58 select TARGET_SOCFPGA_CYCLONE5
60 config TARGET_SOCFPGA_SR1500
61 bool "SR1500 (Cyclone V)"
62 select TARGET_SOCFPGA_CYCLONE5
64 config TARGET_SOCFPGA_TERASIC_DE0_NANO
65 bool "Terasic DE0-Nano-Atlas (Cyclone V)"
66 select TARGET_SOCFPGA_CYCLONE5
68 config TARGET_SOCFPGA_TERASIC_DE10_NANO
69 bool "Terasic DE10-Nano (Cyclone V)"
70 select TARGET_SOCFPGA_CYCLONE5
72 config TARGET_SOCFPGA_TERASIC_DE1_SOC
73 bool "Terasic DE1-SoC (Cyclone V)"
74 select TARGET_SOCFPGA_CYCLONE5
76 config TARGET_SOCFPGA_TERASIC_SOCKIT
77 bool "Terasic SoCkit (Cyclone V)"
78 select TARGET_SOCFPGA_CYCLONE5
83 default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
84 default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
85 default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
86 default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
87 default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
88 default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
89 default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
90 default "is1" if TARGET_SOCFPGA_IS1
91 default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
92 default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
93 default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
94 default "sr1500" if TARGET_SOCFPGA_SR1500
95 default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
98 default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
99 default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
100 default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
101 default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
102 default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
103 default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
104 default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
105 default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
106 default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
107 default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
108 default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
113 config SYS_CONFIG_NAME
114 default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
115 default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
116 default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
117 default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
118 default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
119 default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
120 default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
121 default "socfpga_is1" if TARGET_SOCFPGA_IS1
122 default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
123 default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
124 default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
125 default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
126 default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA