git.sur5r.net Git - u-boot/blob - arch/arm/mach-socfpga/Kconfig

   1 if ARCH_SOCFPGA
   2
   3 config SPL_LIBCOMMON_SUPPORT
   4         default y
   5
   6 config SPL_LIBDISK_SUPPORT
   7         default y
   8
   9 config SPL_LIBGENERIC_SUPPORT
  10         default y
  11
  12 config TARGET_SOCFPGA_ARRIA5
  13         bool
  14         select TARGET_SOCFPGA_GEN5
  15
  16 config TARGET_SOCFPGA_CYCLONE5
  17         bool
  18         select TARGET_SOCFPGA_GEN5
  19
  20 config TARGET_SOCFPGA_GEN5
  21         bool
  22
  23 choice
  24         prompt "Altera SOCFPGA board select"
  25         optional
  26
  27 config TARGET_SOCFPGA_ARRIA5_SOCDK
  28         bool "Altera SOCFPGA SoCDK (Arria V)"
  29         select TARGET_SOCFPGA_ARRIA5
  30
  31 config TARGET_SOCFPGA_CYCLONE5_SOCDK
  32         bool "Altera SOCFPGA SoCDK (Cyclone V)"
  33         select TARGET_SOCFPGA_CYCLONE5
  34
  35 config TARGET_SOCFPGA_DENX_MCVEVK
  36         bool "DENX MCVEVK (Cyclone V)"
  37         select TARGET_SOCFPGA_CYCLONE5
  38
  39 config TARGET_SOCFPGA_EBV_SOCRATES
  40         bool "EBV SoCrates (Cyclone V)"
  41         select TARGET_SOCFPGA_CYCLONE5
  42
  43 config TARGET_SOCFPGA_IS1
  44         bool "IS1 (Cyclone V)"
  45         select TARGET_SOCFPGA_CYCLONE5
  46
  47 config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
  48         bool "samtec VIN|ING FPGA (Cyclone V)"
  49         select TARGET_SOCFPGA_CYCLONE5
  50
  51 config TARGET_SOCFPGA_SR1500
  52         bool "SR1500 (Cyclone V)"
  53         select TARGET_SOCFPGA_CYCLONE5
  54
  55 config TARGET_SOCFPGA_TERASIC_DE0_NANO
  56         bool "Terasic DE0-Nano-Atlas (Cyclone V)"
  57         select TARGET_SOCFPGA_CYCLONE5
  58
  59 config TARGET_SOCFPGA_TERASIC_SOCKIT
  60         bool "Terasic SoCkit (Cyclone V)"
  61         select TARGET_SOCFPGA_CYCLONE5
  62
  63 endchoice
  64
  65 config SYS_BOARD
  66         default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
  67         default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
  68         default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
  69         default "is1" if TARGET_SOCFPGA_IS1
  70         default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
  71         default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
  72         default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
  73         default "sr1500" if TARGET_SOCFPGA_SR1500
  74         default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
  75
  76 config SYS_VENDOR
  77         default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
  78         default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
  79         default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
  80         default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
  81         default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
  82         default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
  83         default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
  84
  85 config SYS_SOC
  86         default "socfpga"
  87
  88 config SYS_CONFIG_NAME
  89         default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
  90         default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
  91         default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
  92         default "socfpga_is1" if TARGET_SOCFPGA_IS1
  93         default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
  94         default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
  95         default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
  96         default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
  97         default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
  98
  99 endif