1 // SPDX-License-Identifier: GPL-2.0+
3 * Altera SoCFPGA common board code
5 * Copyright (C) 2015 Marek Vasut <marex@denx.de>
11 #include <asm/arch/reset_manager.h>
12 #include <asm/arch/clock_manager.h>
16 #include <usb/dwc2_udc.h>
18 DECLARE_GLOBAL_DATA_PTR;
23 * Miscellaneous platform dependent initialisations
27 /* Address of boot parameters for ATAG (if ATAG is used) */
28 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
30 #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
31 /* configuring the clock based on handoff */
32 cm_basic_init(gd->fdt_blob);
38 int dram_init_banksize(void)
40 fdtdec_setup_memory_banksize();
45 #ifdef CONFIG_USB_GADGET
46 struct dwc2_plat_otg_data socfpga_otg_data = {
47 .usb_gusbcfg = 0x1417,
50 int board_usb_init(int index, enum usb_init_type init)
55 count = fdtdec_find_aliases_for_id(gd->fdt_blob, "udc",
56 COMPAT_ALTERA_SOCFPGA_DWC2USB,
58 if (count <= 0) /* No controller found. */
61 addr = fdtdec_get_addr(gd->fdt_blob, node[0], "reg");
62 if (addr == FDT_ADDR_T_NONE) {
63 printf("UDC Controller has no 'reg' property!\n");
67 /* Patch the address from OF into the controller pdata. */
68 socfpga_otg_data.regs_otg = addr;
70 return dwc2_udc_probe(&socfpga_otg_data);
73 int g_dnl_board_usb_cable_connected(void)