2 * Copyright (C) 2016-2017 Intel Corporation
4 * SPDX-License-Identifier: GPL-2.0
7 #ifndef _RESET_MANAGER_ARRIA10_H_
8 #define _RESET_MANAGER_ARRIA10_H_
10 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
12 void socfpga_watchdog_disable(void);
13 void socfpga_reset_deassert_noc_ddr_scheduler(void);
14 int socfpga_is_wdt_in_reset(void);
15 void socfpga_emac_manage_reset(ulong emacbase, u32 state);
16 int socfpga_reset_deassert_bridges_handoff(void);
17 void socfpga_reset_assert_fpga_connected_peripherals(void);
18 void socfpga_reset_deassert_osc1wd0(void);
19 void socfpga_reset_uart(int assert);
20 int socfpga_bridges_reset(int enable);
22 struct socfpga_reset_manager {
58 * SocFPGA Arria10 reset IDs, bank mapping is as follows:
65 #define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0)
66 #define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1)
67 #define RSTMGR_EMAC2 RSTMGR_DEFINE(1, 2)
68 #define RSTMGR_NAND RSTMGR_DEFINE(1, 5)
69 #define RSTMGR_QSPI RSTMGR_DEFINE(1, 6)
70 #define RSTMGR_SDMMC RSTMGR_DEFINE(1, 7)
71 #define RSTMGR_DMA RSTMGR_DEFINE(1, 16)
72 #define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 17)
73 #define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 18)
74 #define RSTMGR_L4WD0 RSTMGR_DEFINE(2, 0)
75 #define RSTMGR_L4WD1 RSTMGR_DEFINE(2, 1)
76 #define RSTMGR_L4SYSTIMER0 RSTMGR_DEFINE(2, 2)
77 #define RSTMGR_L4SYSTIMER1 RSTMGR_DEFINE(2, 3)
78 #define RSTMGR_SPTIMER0 RSTMGR_DEFINE(2, 4)
79 #define RSTMGR_SPTIMER1 RSTMGR_DEFINE(2, 5)
80 #define RSTMGR_UART0 RSTMGR_DEFINE(2, 16)
81 #define RSTMGR_UART1 RSTMGR_DEFINE(2, 17)
82 #define RSTMGR_DDRSCH RSTMGR_DEFINE(3, 6)
84 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSK BIT(1)
85 #define ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK BIT(0)
86 #define ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK BIT(1)
87 #define ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK BIT(2)
88 #define ALT_RSTMGR_PER0MODRST_USB0_SET_MSK BIT(3)
89 #define ALT_RSTMGR_PER0MODRST_USB1_SET_MSK BIT(4)
90 #define ALT_RSTMGR_PER0MODRST_NAND_SET_MSK BIT(5)
91 #define ALT_RSTMGR_PER0MODRST_QSPI_SET_MSK BIT(6)
92 #define ALT_RSTMGR_PER0MODRST_SDMMC_SET_MSK BIT(7)
93 #define ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK BIT(8)
94 #define ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK BIT(9)
95 #define ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK BIT(10)
96 #define ALT_RSTMGR_PER0MODRST_USBECC0_SET_MSK BIT(11)
97 #define ALT_RSTMGR_PER0MODRST_USBECC1_SET_MSK BIT(12)
98 #define ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK BIT(13)
99 #define ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK BIT(14)
100 #define ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK BIT(15)
101 #define ALT_RSTMGR_PER0MODRST_DMA_SET_MSK BIT(16)
102 #define ALT_RSTMGR_PER0MODRST_SPIM0_SET_MSK BIT(17)
103 #define ALT_RSTMGR_PER0MODRST_SPIM1_SET_MSK BIT(18)
104 #define ALT_RSTMGR_PER0MODRST_SPIS0_SET_MSK BIT(19)
105 #define ALT_RSTMGR_PER0MODRST_SPIS1_SET_MSK BIT(20)
106 #define ALT_RSTMGR_PER0MODRST_DMAECC_SET_MSK BIT(21)
107 #define ALT_RSTMGR_PER0MODRST_EMACPTP_SET_MSK BIT(22)
108 #define ALT_RSTMGR_PER0MODRST_DMAIF0_SET_MSK BIT(24)
109 #define ALT_RSTMGR_PER0MODRST_DMAIF1_SET_MSK BIT(25)
110 #define ALT_RSTMGR_PER0MODRST_DMAIF2_SET_MSK BIT(26)
111 #define ALT_RSTMGR_PER0MODRST_DMAIF3_SET_MSK BIT(27)
112 #define ALT_RSTMGR_PER0MODRST_DMAIF4_SET_MSK BIT(28)
113 #define ALT_RSTMGR_PER0MODRST_DMAIF5_SET_MSK BIT(29)
114 #define ALT_RSTMGR_PER0MODRST_DMAIF6_SET_MSK BIT(30)
115 #define ALT_RSTMGR_PER0MODRST_DMAIF7_SET_MSK BIT(31)
117 #define ALT_RSTMGR_PER1MODRST_WD0_SET_MSK BIT(0)
118 #define ALT_RSTMGR_PER1MODRST_WD1_SET_MSK BIT(1)
119 #define ALT_RSTMGR_PER1MODRST_L4SYSTMR0_SET_MSK BIT(2)
120 #define ALT_RSTMGR_PER1MODRST_L4SYSTMR1_SET_MSK BIT(3)
121 #define ALT_RSTMGR_PER1MODRST_SPTMR0_SET_MSK BIT(4)
122 #define ALT_RSTMGR_PER1MODRST_SPTMR1_SET_MSK BIT(5)
123 #define ALT_RSTMGR_PER1MODRST_I2C0_SET_MSK BIT(8)
124 #define ALT_RSTMGR_PER1MODRST_I2C1_SET_MSK BIT(9)
125 #define ALT_RSTMGR_PER1MODRST_I2C2_SET_MSK BIT(10)
126 #define ALT_RSTMGR_PER1MODRST_I2C3_SET_MSK BIT(11)
127 #define ALT_RSTMGR_PER1MODRST_I2C4_SET_MSK BIT(12)
128 #define ALT_RSTMGR_PER1MODRST_UART0_SET_MSK BIT(16)
129 #define ALT_RSTMGR_PER1MODRST_UART1_SET_MSK BIT(17)
130 #define ALT_RSTMGR_PER1MODRST_GPIO0_SET_MSK BIT(24)
131 #define ALT_RSTMGR_PER1MODRST_GPIO1_SET_MSK BIT(25)
132 #define ALT_RSTMGR_PER1MODRST_GPIO2_SET_MSK BIT(26)
134 #define ALT_RSTMGR_BRGMODRST_H2F_SET_MSK BIT(0)
135 #define ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK BIT(1)
136 #define ALT_RSTMGR_BRGMODRST_F2H_SET_MSK BIT(2)
137 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK BIT(3)
138 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK BIT(4)
139 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK BIT(5)
140 #define ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK BIT(6)
142 #define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_SET_MSK BIT(0)
143 #define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_SET_MSK BIT(1)
144 #define ALT_RSTMGR_HDSKEN_FPGAHSEN_SET_MSK BIT(2)
145 #define ALT_RSTMGR_HDSKEN_ETRSTALLEN_SET_MSK BIT(3)
147 #endif /* _RESET_MANAGER_ARRIA10_H_ */