2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/reset_manager.h>
14 #include <asm/arch/system_manager.h>
15 #include <asm/arch/dwmmc.h>
16 #include <asm/arch/nic301.h>
17 #include <asm/arch/scu.h>
18 #include <asm/pl310.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 static struct pl310_regs *const pl310 =
23 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
24 static struct socfpga_system_manager *sysmgr_regs =
25 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
26 static struct socfpga_reset_manager *reset_manager_base =
27 (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
28 static struct nic301_registers *nic301_regs =
29 (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
30 static struct scu_registers *scu_regs =
31 (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
35 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
39 void enable_caches(void)
41 #ifndef CONFIG_SYS_ICACHE_OFF
44 #ifndef CONFIG_SYS_DCACHE_OFF
50 * DesignWare Ethernet initialization
52 #ifdef CONFIG_ETH_DESIGNWARE
53 int cpu_eth_init(bd_t *bis)
55 #if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS
56 const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
57 const u32 reset = SOCFPGA_RESET(EMAC0);
58 #elif CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS
59 const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
60 const u32 reset = SOCFPGA_RESET(EMAC1);
62 #error "Incorrect CONFIG_EMAC_BASE value!"
65 /* Initialize EMAC. This needs to be done at least once per boot. */
68 * Putting the EMAC controller to reset when configuring the PHY
69 * interface select at System Manager
71 socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
72 socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
74 /* Clearing emac0 PHY interface select to 0 */
75 clrbits_le32(&sysmgr_regs->emacgrp_ctrl,
76 SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
78 /* configure to PHY interface select choosed */
79 setbits_le32(&sysmgr_regs->emacgrp_ctrl,
80 SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
82 /* Release the EMAC controller from reset */
83 socfpga_per_reset(reset, 0);
91 * Initializes MMC controllers.
92 * to override, implement board_mmc_init()
94 int cpu_mmc_init(bd_t *bis)
96 return socfpga_dwmmc_init(SOCFPGA_SDMMC_ADDRESS,
97 CONFIG_HPS_SDMMC_BUSWIDTH, 0);
105 { "rsvd", "Reserved", },
106 { "fpga", "FPGA (HPS2FPGA Bridge)", },
107 { "nand", "NAND Flash (1.8V)", },
108 { "nand", "NAND Flash (3.0V)", },
109 { "sd", "SD/MMC External Transceiver (1.8V)", },
110 { "sd", "SD/MMC Internal Transceiver (3.0V)", },
111 { "qspi", "QSPI Flash (1.8V)", },
112 { "qspi", "QSPI Flash (3.0V)", },
116 * Print CPU information
118 #if defined(CONFIG_DISPLAY_CPUINFO)
119 int print_cpuinfo(void)
121 const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
122 puts("CPU: Altera SoCFPGA Platform\n");
123 printf("BOOT: %s\n", bsel_str[bsel].name);
128 #ifdef CONFIG_ARCH_MISC_INIT
129 int arch_misc_init(void)
131 const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
132 setenv("bootmode", bsel_str[bsel].mode);
137 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
138 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
139 int overwrite_console(void)
147 * FPGA programming support for SoC FPGA Cyclone V
149 static Altera_desc altera_fpga[] = {
154 fast_passive_parallel,
155 /* No limitation as additional data will be ignored */
157 /* No device function table */
159 /* Base interface address specified in driver */
161 /* No cookie implementation */
166 /* add device descriptor to FPGA device table */
167 static void socfpga_fpga_add(void)
171 for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
172 fpga_add(fpga_altera, &altera_fpga[i]);
175 static inline void socfpga_fpga_add(void) {}
178 int arch_cpu_init(void)
180 #ifdef CONFIG_HW_WATCHDOG
182 * In case the watchdog is enabled, make sure to (re-)configure it
183 * so that the defined timeout is valid. Otherwise the SPL (Perloader)
184 * timeout value is still active which might too short for Linux
190 * If the HW watchdog is NOT enabled, make sure it is not running,
191 * for example because it was enabled in the preloader. This might
192 * trigger a watchdog-triggered reboot of Linux kernel later.
193 * Toggle watchdog reset, so watchdog in not running state.
195 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
196 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
203 * Convert all NIC-301 AMBA slaves from secure to non-secure
205 static void socfpga_nic301_slave_ns(void)
207 writel(0x1, &nic301_regs->lwhps2fpgaregs);
208 writel(0x1, &nic301_regs->hps2fpgaregs);
209 writel(0x1, &nic301_regs->acp);
210 writel(0x1, &nic301_regs->rom);
211 writel(0x1, &nic301_regs->ocram);
212 writel(0x1, &nic301_regs->sdrdata);
215 static uint32_t iswgrp_handoff[8];
217 int arch_early_init_r(void)
222 * Write magic value into magic register to unlock support for
223 * issuing warm reset. The ancient kernel code expects this
224 * value to be written into the register by the bootloader, so
225 * to support that old code, we write it here instead of in the
226 * reset_cpu() function just before reseting the CPU.
228 writel(0xae9efebc, &sysmgr_regs->romcodegrp_warmramgrp_enable);
230 for (i = 0; i < 8; i++) /* Cache initial SW setting regs */
231 iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
233 socfpga_bridges_reset(1);
234 socfpga_nic301_slave_ns();
237 * Private components security:
238 * U-Boot : configure private timer, global timer and cpu component
239 * access as non secure for kernel stage (as required by Linux)
241 setbits_le32(&scu_regs->sacr, 0xfff);
243 /* Configure the L2 controller to make SDRAM start at 0 */
244 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
245 writel(0x2, &nic301_regs->remap);
247 writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
248 writel(0x1, &pl310->pl310_addr_filter_start);
251 /* Add device descriptor to FPGA device table */
254 #ifdef CONFIG_DESIGNWARE_SPI
255 /* Get Designware SPI controller out of reset */
256 socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0);
257 socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);
263 static void socfpga_sdram_apply_static_cfg(void)
265 const uint32_t staticcfg = SOCFPGA_SDR_ADDRESS + 0x505c;
266 const uint32_t applymask = 0x8;
267 uint32_t val = readl(staticcfg) | applymask;
270 * SDRAM staticcfg register specific:
271 * When applying the register setting, the CPU must not access
272 * SDRAM. Luckily for us, we can abuse i-cache here to help us
273 * circumvent the SDRAM access issue. The idea is to make sure
274 * that the code is in one full i-cache line by branching past
275 * it and back. Once it is in the i-cache, we execute the core
276 * of the code and apply the register settings.
278 * The code below uses 7 instructions, while the Cortex-A9 has
279 * 32-byte cachelines, thus the limit is 8 instructions total.
290 : : "r"(val), "r"(staticcfg) : "memory", "cc");
293 int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
296 return CMD_RET_USAGE;
301 case 'e': /* Enable */
302 writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
303 socfpga_sdram_apply_static_cfg();
304 writel(iswgrp_handoff[3], SOCFPGA_SDR_ADDRESS + 0x5080);
305 writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
306 writel(iswgrp_handoff[1], &nic301_regs->remap);
308 case 'd': /* Disable */
309 writel(0, &sysmgr_regs->fpgaintfgrp_module);
310 writel(0, SOCFPGA_SDR_ADDRESS + 0x5080);
311 socfpga_sdram_apply_static_cfg();
312 writel(0, &reset_manager_base->brg_mod_reset);
313 writel(1, &nic301_regs->remap);
316 return CMD_RET_USAGE;
323 bridge, 2, 1, do_bridge,
324 "SoCFPGA HPS FPGA bridge control",
325 "enable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
326 "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"