1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
10 #include <linux/libfdt.h>
15 #include <asm/arch/misc.h>
16 #include <asm/arch/reset_manager.h>
17 #include <asm/arch/scan_manager.h>
18 #include <asm/arch/system_manager.h>
19 #include <asm/arch/nic301.h>
20 #include <asm/arch/scu.h>
21 #include <asm/pl310.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 static const struct pl310_regs *const pl310 =
26 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
28 struct bsel bsel_str[] = {
29 { "rsvd", "Reserved", },
30 { "fpga", "FPGA (HPS2FPGA Bridge)", },
31 { "nand", "NAND Flash (1.8V)", },
32 { "nand", "NAND Flash (3.0V)", },
33 { "sd", "SD/MMC External Transceiver (1.8V)", },
34 { "sd", "SD/MMC Internal Transceiver (3.0V)", },
35 { "qspi", "QSPI Flash (1.8V)", },
36 { "qspi", "QSPI Flash (3.0V)", },
41 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
45 void enable_caches(void)
47 #ifndef CONFIG_SYS_ICACHE_OFF
50 #ifndef CONFIG_SYS_DCACHE_OFF
55 void v7_outer_cache_enable(void)
57 /* Disable the L2 cache */
58 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
60 /* enable BRESP, instruction and data prefetch, full line of zeroes */
61 setbits_le32(&pl310->pl310_aux_ctrl,
62 L310_AUX_CTRL_DATA_PREFETCH_MASK |
63 L310_AUX_CTRL_INST_PREFETCH_MASK |
64 L310_SHARED_ATT_OVERRIDE_ENABLE);
66 /* Enable the L2 cache */
67 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
70 void v7_outer_cache_disable(void)
72 /* Disable the L2 cache */
73 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
76 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
77 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
78 int overwrite_console(void)
86 * FPGA programming support for SoC FPGA Cyclone V
88 static Altera_desc altera_fpga[] = {
93 fast_passive_parallel,
94 /* No limitation as additional data will be ignored */
96 /* No device function table */
98 /* Base interface address specified in driver */
100 /* No cookie implementation */
105 /* add device descriptor to FPGA device table */
106 void socfpga_fpga_add(void)
110 for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
111 fpga_add(fpga_altera, &altera_fpga[i]);
115 int arch_cpu_init(void)
117 #ifdef CONFIG_HW_WATCHDOG
119 * In case the watchdog is enabled, make sure to (re-)configure it
120 * so that the defined timeout is valid. Otherwise the SPL (Perloader)
121 * timeout value is still active which might too short for Linux
127 * If the HW watchdog is NOT enabled, make sure it is not running,
128 * for example because it was enabled in the preloader. This might
129 * trigger a watchdog-triggered reboot of Linux kernel later.
130 * Toggle watchdog reset, so watchdog in not running state.
132 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
133 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);