2 * Copyright (C) 2013 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/reset_manager.h>
11 #include <asm/arch/fpga_manager.h>
13 DECLARE_GLOBAL_DATA_PTR;
15 static const struct socfpga_reset_manager *reset_manager_base =
16 (void *)SOCFPGA_RSTMGR_ADDRESS;
18 /* Assert or de-assert SoCFPGA reset manager reset. */
19 void socfpga_per_reset(u32 reset, int set)
23 if (RSTMGR_BANK(reset) == 0)
24 reg = &reset_manager_base->mpu_mod_reset;
25 else if (RSTMGR_BANK(reset) == 1)
26 reg = &reset_manager_base->per_mod_reset;
27 else if (RSTMGR_BANK(reset) == 2)
28 reg = &reset_manager_base->per2_mod_reset;
29 else if (RSTMGR_BANK(reset) == 3)
30 reg = &reset_manager_base->brg_mod_reset;
31 else if (RSTMGR_BANK(reset) == 4)
32 reg = &reset_manager_base->misc_mod_reset;
33 else /* Invalid reset register, do nothing */
37 setbits_le32(reg, 1 << RSTMGR_RESET(reset));
39 clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
43 * Write the reset manager register to cause reset
45 void reset_cpu(ulong addr)
47 /* request a warm reset */
48 writel((1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB),
49 &reset_manager_base->ctrl);
51 * infinite loop here as watchdog will trigger and reset
59 * Release peripherals from reset based on handoff
61 void reset_deassert_peripherals_handoff(void)
63 writel(0, &reset_manager_base->per_mod_reset);
66 #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
67 void socfpga_bridges_reset(int enable)
69 /* For SoCFPGA-VT, this is NOP. */
73 #define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10
74 #define L3REGS_REMAP_HPS2FPGA_MASK 0x08
75 #define L3REGS_REMAP_OCRAM_MASK 0x01
77 void socfpga_bridges_reset(int enable)
79 const uint32_t l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
80 L3REGS_REMAP_HPS2FPGA_MASK |
81 L3REGS_REMAP_OCRAM_MASK;
85 writel(0xffffffff, &reset_manager_base->brg_mod_reset);
87 /* Check signal from FPGA. */
88 if (fpgamgr_poll_fpga_ready()) {
89 /* FPGA not ready. Wait for watchdog timeout. */
90 printf("%s: fpga not ready, hanging.\n", __func__);
95 writel(0, &reset_manager_base->brg_mod_reset);
97 /* Remap the bridges into memory map */
98 writel(l3mask, SOCFPGA_L3REGS_ADDRESS);