2 * Copyright (C) 2013 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/reset_manager.h>
11 #include <asm/arch/fpga_manager.h>
13 DECLARE_GLOBAL_DATA_PTR;
15 static const struct socfpga_reset_manager *reset_manager_base =
16 (void *)SOCFPGA_RSTMGR_ADDRESS;
18 /* Assert or de-assert SoCFPGA reset manager reset. */
19 void socfpga_per_reset(u32 reset, int set)
23 if (RSTMGR_BANK(reset) == 0)
24 reg = &reset_manager_base->mpu_mod_reset;
25 else if (RSTMGR_BANK(reset) == 1)
26 reg = &reset_manager_base->per_mod_reset;
27 else if (RSTMGR_BANK(reset) == 2)
28 reg = &reset_manager_base->per2_mod_reset;
29 else if (RSTMGR_BANK(reset) == 3)
30 reg = &reset_manager_base->brg_mod_reset;
31 else if (RSTMGR_BANK(reset) == 4)
32 reg = &reset_manager_base->misc_mod_reset;
33 else /* Invalid reset register, do nothing */
37 setbits_le32(reg, 1 << RSTMGR_RESET(reset));
39 clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
42 /* Toggle reset signal to watchdog (WDT is disabled after this operation!) */
43 void socfpga_watchdog_reset(void)
45 /* assert reset for watchdog */
46 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
48 /* deassert watchdog from reset (watchdog in not running state) */
49 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
53 * Write the reset manager register to cause reset
55 void reset_cpu(ulong addr)
57 /* request a warm reset */
58 writel((1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB),
59 &reset_manager_base->ctrl);
61 * infinite loop here as watchdog will trigger and reset
69 * Release peripherals from reset based on handoff
71 void reset_deassert_peripherals_handoff(void)
73 writel(0, &reset_manager_base->per_mod_reset);
76 #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
77 void socfpga_bridges_reset(int enable)
79 /* For SoCFPGA-VT, this is NOP. */
83 #define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10
84 #define L3REGS_REMAP_HPS2FPGA_MASK 0x08
85 #define L3REGS_REMAP_OCRAM_MASK 0x01
87 void socfpga_bridges_reset(int enable)
89 const uint32_t l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
90 L3REGS_REMAP_HPS2FPGA_MASK |
91 L3REGS_REMAP_OCRAM_MASK;
95 writel(0xffffffff, &reset_manager_base->brg_mod_reset);
97 /* Check signal from FPGA. */
98 if (fpgamgr_poll_fpga_ready()) {
99 /* FPGA not ready. Wait for watchdog timeout. */
100 printf("%s: fpga not ready, hanging.\n", __func__);
105 writel(0, &reset_manager_base->brg_mod_reset);
107 /* Remap the bridges into memory map */
108 writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
113 /* Change the reset state for EMAC 0 and EMAC 1 */
114 void socfpga_emac_reset(int enable)
117 socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
118 socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
120 #if (CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS)
121 socfpga_per_reset(SOCFPGA_RESET(EMAC0), 0);
122 #elif (CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS)
123 socfpga_per_reset(SOCFPGA_RESET(EMAC1), 0);
128 /* SPI Master enable (its held in reset by the preloader) */
129 void socfpga_spim_enable(void)
131 socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0);
132 socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);
135 /* Bring UART0 out of reset. */
136 void socfpga_uart0_enable(void)
138 socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
141 /* Bring SDRAM controller out of reset. */
142 void socfpga_sdram_enable(void)
144 socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
147 /* Bring OSC1 timer out of reset. */
148 void socfpga_osc1timer_enable(void)
150 socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);