git.sur5r.net Git - u-boot/blob - arch/arm/mach-socfpga/reset_manager.c

   1 /*
   2  *  Copyright (C) 2013 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/reset_manager.h>
  11 #include <asm/arch/fpga_manager.h>
  12
  13 DECLARE_GLOBAL_DATA_PTR;
  14
  15 static const struct socfpga_reset_manager *reset_manager_base =
  16                 (void *)SOCFPGA_RSTMGR_ADDRESS;
  17
  18 /* Assert or de-assert SoCFPGA reset manager reset. */
  19 void socfpga_per_reset(u32 reset, int set)
  20 {
  21         const void *reg;
  22
  23         if (RSTMGR_BANK(reset) == 0)
  24                 reg = &reset_manager_base->mpu_mod_reset;
  25         else if (RSTMGR_BANK(reset) == 1)
  26                 reg = &reset_manager_base->per_mod_reset;
  27         else if (RSTMGR_BANK(reset) == 2)
  28                 reg = &reset_manager_base->per2_mod_reset;
  29         else if (RSTMGR_BANK(reset) == 3)
  30                 reg = &reset_manager_base->brg_mod_reset;
  31         else if (RSTMGR_BANK(reset) == 4)
  32                 reg = &reset_manager_base->misc_mod_reset;
  33         else    /* Invalid reset register, do nothing */
  34                 return;
  35
  36         if (set)
  37                 setbits_le32(reg, 1 << RSTMGR_RESET(reset));
  38         else
  39                 clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
  40 }
  41
  42 /*
  43  * Write the reset manager register to cause reset
  44  */
  45 void reset_cpu(ulong addr)
  46 {
  47         /* request a warm reset */
  48         writel((1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB),
  49                 &reset_manager_base->ctrl);
  50         /*
  51          * infinite loop here as watchdog will trigger and reset
  52          * the processor
  53          */
  54         while (1)
  55                 ;
  56 }
  57
  58 /*
  59  * Release peripherals from reset based on handoff
  60  */
  61 void reset_deassert_peripherals_handoff(void)
  62 {
  63         writel(0, &reset_manager_base->per_mod_reset);
  64 }
  65
  66 #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
  67 void socfpga_bridges_reset(int enable)
  68 {
  69         /* For SoCFPGA-VT, this is NOP. */
  70 }
  71 #else
  72
  73 #define L3REGS_REMAP_LWHPS2FPGA_MASK    0x10
  74 #define L3REGS_REMAP_HPS2FPGA_MASK      0x08
  75 #define L3REGS_REMAP_OCRAM_MASK         0x01
  76
  77 void socfpga_bridges_reset(int enable)
  78 {
  79         const uint32_t l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
  80                                 L3REGS_REMAP_HPS2FPGA_MASK |
  81                                 L3REGS_REMAP_OCRAM_MASK;
  82
  83         if (enable) {
  84                 /* brdmodrst */
  85                 writel(0xffffffff, &reset_manager_base->brg_mod_reset);
  86         } else {
  87                 /* Check signal from FPGA. */
  88                 if (!fpgamgr_test_fpga_ready()) {
  89                         /* FPGA not ready, do nothing. */
  90                         printf("%s: FPGA not ready, aborting.\n", __func__);
  91                         return;
  92                 }
  93
  94                 /* brdmodrst */
  95                 writel(0, &reset_manager_base->brg_mod_reset);
  96
  97                 /* Remap the bridges into memory map */
  98                 writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
  99         }
 100 }
 101 #endif