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[u-boot] / arch / arm / mach-stm32 / stm32f7 / soc.c
1 /*
2  * (C) Copyright 2015
3  * Kamil Lulko, <kamil.lulko@gmail.com>
4  *
5  * SPDX-License-Identifier:     GPL-2.0+
6  */
7
8 #include <common.h>
9 #include <asm/io.h>
10 #include <asm/armv7m.h>
11 #include <asm/arch/stm32.h>
12
13 u32 get_cpu_rev(void)
14 {
15         return 0;
16 }
17
18 int arch_cpu_init(void)
19 {
20         /*
21                 * Configure the memory protection unit (MPU)
22                 * 0x00000000 - 0xffffffff: Strong-order, Shareable
23                 * 0xC0000000 - 0xC0800000: Normal, Outer and inner Non-cacheable
24          */
25
26          /* Disable MPU */
27          writel(0, &V7M_MPU->ctrl);
28
29          writel(
30                  0x00000000 /* address */
31                  | 1 << 4       /* VALID */
32                  | 0 << 0       /* REGION */
33                  , &V7M_MPU->rbar
34          );
35
36          /* Strong-order, Shareable */
37          /* TEX=000, S=1, C=0, B=0*/
38          writel(
39                  (V7M_MPU_RASR_XN_ENABLE
40                          | V7M_MPU_RASR_AP_RW_RW
41                          | 0x01 << V7M_MPU_RASR_S_SHIFT
42                          | 0x00 << V7M_MPU_RASR_TEX_SHIFT
43                          | V7M_MPU_RASR_SIZE_4GB
44                          | V7M_MPU_RASR_EN)
45                  , &V7M_MPU->rasr
46          );
47
48          writel(
49                  0xC0000000 /* address */
50                  | 1 << 4       /* VALID */
51                  | 1 << 0       /* REGION */
52                  , &V7M_MPU->rbar
53          );
54
55          /* Normal, Outer and inner Non-cacheable */
56          /* TEX=001, S=0, C=0, B=0*/
57          writel(
58                  (V7M_MPU_RASR_XN_ENABLE
59                          | V7M_MPU_RASR_AP_RW_RW
60                          | 0x01 << V7M_MPU_RASR_TEX_SHIFT
61                          | V7M_MPU_RASR_SIZE_8MB
62                          | V7M_MPU_RASR_EN)
63                          , &V7M_MPU->rasr
64          );
65
66          /* Enable MPU */
67          writel(V7M_MPU_CTRL_ENABLE | V7M_MPU_CTRL_HFNMIENA, &V7M_MPU->ctrl);
68
69         return 0;
70 }
71
72 void s_init(void)
73 {
74 }