4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
7 default " Allwinner Technology"
13 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
14 with the first SRAM region being located at address 0.
15 Some newer SoCs map the boot ROM at address 0 instead and move the
16 SRAM to 64KB, just behind the mask ROM.
17 Chips using the latter setup are supposed to select this option to
18 adjust the addresses accordingly.
20 # Note only one of these may be selected at a time! But hidden choices are
21 # not supported by Kconfig
22 config SUNXI_GEN_SUN4I
25 Select this for sunxi SoCs which have resets and clocks set up
26 as the original A10 (mach-sun4i).
28 config SUNXI_GEN_SUN6I
31 Select this for sunxi SoCs which have sun6i like periphery, like
32 separate ahb reset control registers, custom pmic bus, new style
38 Select this for sunxi SoCs which uses a DRAM controller like the
39 DesignWare controller used in H3, mainly SoCs after H3, which do
40 not have official open-source DRAM initialization code, but can
41 use modified H3 DRAM initialization code.
44 config SUNXI_DRAM_DW_16BIT
47 Select this for sunxi SoCs with DesignWare DRAM controller and
48 have only 16-bit memory buswidth.
50 config SUNXI_DRAM_DW_32BIT
53 Select this for sunxi SoCs with DesignWare DRAM controller with
54 32-bit memory buswidth.
57 config MACH_SUNXI_H3_H5
62 select SUNXI_DRAM_DW_32BIT
63 select SUNXI_GEN_SUN6I
67 prompt "Sunxi SoC Variant"
71 bool "sun4i (Allwinner A10)"
73 select ARM_CORTEX_CPU_IS_UP
74 select SUNXI_GEN_SUN4I
78 bool "sun5i (Allwinner A13)"
80 select ARM_CORTEX_CPU_IS_UP
81 select SUNXI_GEN_SUN4I
83 imply CONS_INDEX_2 if !DM_SERIAL
86 bool "sun6i (Allwinner A31)"
88 select CPU_V7_HAS_NONSEC
89 select CPU_V7_HAS_VIRT
90 select ARCH_SUPPORT_PSCI
91 select SUNXI_GEN_SUN6I
93 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
96 bool "sun7i (Allwinner A20)"
98 select CPU_V7_HAS_NONSEC
99 select CPU_V7_HAS_VIRT
100 select ARCH_SUPPORT_PSCI
101 select SUNXI_GEN_SUN4I
103 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
105 config MACH_SUN8I_A23
106 bool "sun8i (Allwinner A23)"
108 select CPU_V7_HAS_NONSEC
109 select CPU_V7_HAS_VIRT
110 select ARCH_SUPPORT_PSCI
111 select SUNXI_GEN_SUN6I
113 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
114 imply CONS_INDEX_5 if !DM_SERIAL
116 config MACH_SUN8I_A33
117 bool "sun8i (Allwinner A33)"
119 select CPU_V7_HAS_NONSEC
120 select CPU_V7_HAS_VIRT
121 select ARCH_SUPPORT_PSCI
122 select SUNXI_GEN_SUN6I
124 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
125 imply CONS_INDEX_5 if !DM_SERIAL
127 config MACH_SUN8I_A83T
128 bool "sun8i (Allwinner A83T)"
130 select SUNXI_GEN_SUN6I
131 select MMC_SUNXI_HAS_NEW_MODE
135 bool "sun8i (Allwinner H3)"
137 select CPU_V7_HAS_NONSEC
138 select CPU_V7_HAS_VIRT
139 select ARCH_SUPPORT_PSCI
140 select MACH_SUNXI_H3_H5
141 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
143 config MACH_SUN8I_R40
144 bool "sun8i (Allwinner R40)"
146 select CPU_V7_HAS_NONSEC
147 select CPU_V7_HAS_VIRT
148 select ARCH_SUPPORT_PSCI
149 select SUNXI_GEN_SUN6I
152 select SUNXI_DRAM_DW_32BIT
154 config MACH_SUN8I_V3S
155 bool "sun8i (Allwinner V3s)"
157 select CPU_V7_HAS_NONSEC
158 select CPU_V7_HAS_VIRT
159 select ARCH_SUPPORT_PSCI
160 select SUNXI_GEN_SUN6I
162 select SUNXI_DRAM_DW_16BIT
164 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
167 bool "sun9i (Allwinner A80)"
169 select SUNXI_HIGH_SRAM
170 select SUNXI_GEN_SUN6I
174 bool "sun50i (Allwinner A64)"
178 select SUNXI_GEN_SUN6I
179 select SUNXI_HIGH_SRAM
182 select SUNXI_DRAM_DW_32BIT
186 config MACH_SUN50I_H5
187 bool "sun50i (Allwinner H5)"
189 select MACH_SUNXI_H3_H5
190 select SUNXI_HIGH_SRAM
196 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
199 default y if MACH_SUN8I_A23
200 default y if MACH_SUN8I_A33
201 default y if MACH_SUN8I_A83T
202 default y if MACH_SUNXI_H3_H5
203 default y if MACH_SUN8I_R40
204 default y if MACH_SUN8I_V3S
206 config RESERVE_ALLWINNER_BOOT0_HEADER
207 bool "reserve space for Allwinner boot0 header"
208 select ENABLE_ARM_SOC_BOOT0_HOOK
210 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
211 filled with magic values post build. The Allwinner provided boot0
212 blob relies on this information to load and execute U-Boot.
213 Only needed on 64-bit Allwinner boards so far when using boot0.
215 config ARM_BOOT_HOOK_RMR
219 select ENABLE_ARM_SOC_BOOT0_HOOK
221 Insert some ARM32 code at the very beginning of the U-Boot binary
222 which uses an RMR register write to bring the core into AArch64 mode.
223 The very first instruction acts as a switch, since it's carefully
224 chosen to be a NOP in one mode and a branch in the other, so the
225 code would only be executed if not already in AArch64.
226 This allows both the SPL and the U-Boot proper to be entered in
227 either mode and switch to AArch64 if needed.
230 config SUNXI_DRAM_DDR3
233 config SUNXI_DRAM_DDR2
236 config SUNXI_DRAM_LPDDR3
240 prompt "DRAM Type and Timing"
241 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
242 default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
244 config SUNXI_DRAM_DDR3_1333
246 select SUNXI_DRAM_DDR3
247 depends on !MACH_SUN8I_V3S
249 This option is the original only supported memory type, which suits
250 many H3/H5/A64 boards available now.
252 config SUNXI_DRAM_LPDDR3_STOCK
253 bool "LPDDR3 with Allwinner stock configuration"
254 select SUNXI_DRAM_LPDDR3
256 This option is the LPDDR3 timing used by the stock boot0 by
259 config SUNXI_DRAM_DDR2_V3S
260 bool "DDR2 found in V3s chip"
261 select SUNXI_DRAM_DDR2
262 depends on MACH_SUN8I_V3S
264 This option is only for the DDR2 memory chip which is co-packaged in
271 int "sunxi dram type"
272 depends on MACH_SUN8I_A83T
275 Set the dram type, 3: DDR3, 7: LPDDR3
278 int "sunxi dram clock speed"
279 default 792 if MACH_SUN9I
280 default 648 if MACH_SUN8I_R40
281 default 312 if MACH_SUN6I || MACH_SUN8I
282 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
284 default 672 if MACH_SUN50I
286 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
287 must be a multiple of 24. For the sun9i (A80), the tested values
288 (for DDR3-1600) are 312 to 792.
290 if MACH_SUN5I || MACH_SUN7I
292 int "sunxi mbus clock speed"
295 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
300 int "sunxi dram zq value"
301 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
302 default 127 if MACH_SUN7I
303 default 14779 if MACH_SUN8I_V3S
304 default 3881979 if MACH_SUN8I_R40
305 default 4145117 if MACH_SUN9I
306 default 3881915 if MACH_SUN50I
308 Set the dram zq value.
311 bool "sunxi dram odt enable"
312 default n if !MACH_SUN8I_A23
313 default y if MACH_SUN8I_A23
314 default y if MACH_SUN8I_R40
315 default y if MACH_SUN50I
317 Select this to enable dram odt (on die termination).
319 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
321 int "sunxi dram emr1 value"
322 default 0 if MACH_SUN4I
323 default 4 if MACH_SUN5I || MACH_SUN7I
325 Set the dram controller emr1 value.
328 hex "sunxi dram tpr3 value"
331 Set the dram controller tpr3 parameter. This parameter configures
332 the delay on the command lane and also phase shifts, which are
333 applied for sampling incoming read data. The default value 0
334 means that no phase/delay adjustments are necessary. Properly
335 configuring this parameter increases reliability at high DRAM
338 config DRAM_DQS_GATING_DELAY
339 hex "sunxi dram dqs_gating_delay value"
342 Set the dram controller dqs_gating_delay parmeter. Each byte
343 encodes the DQS gating delay for each byte lane. The delay
344 granularity is 1/4 cycle. For example, the value 0x05060606
345 means that the delay is 5 quarter-cycles for one lane (1.25
346 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
347 The default value 0 means autodetection. The results of hardware
348 autodetection are not very reliable and depend on the chip
349 temperature (sometimes producing different results on cold start
350 and warm reboot). But the accuracy of hardware autodetection
351 is usually good enough, unless running at really high DRAM
352 clocks speeds (up to 600MHz). If unsure, keep as 0.
355 prompt "sunxi dram timings"
356 default DRAM_TIMINGS_VENDOR_MAGIC
358 Select the timings of the DDR3 chips.
360 config DRAM_TIMINGS_VENDOR_MAGIC
361 bool "Magic vendor timings from Android"
363 The same DRAM timings as in the Allwinner boot0 bootloader.
365 config DRAM_TIMINGS_DDR3_1066F_1333H
366 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
368 Use the timings of the standard JEDEC DDR3-1066F speed bin for
369 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
370 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
371 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
372 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
373 that down binning to DDR3-1066F is supported (because DDR3-1066F
374 uses a bit faster timings than DDR3-1333H).
376 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
377 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
379 Use the timings of the slowest possible JEDEC speed bin for the
380 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
381 DDR3-800E, DDR3-1066G or DDR3-1333J.
388 config DRAM_ODT_CORRECTION
389 int "sunxi dram odt correction value"
392 Set the dram odt correction value (range -255 - 255). In allwinner
393 fex files, this option is found in bits 8-15 of the u32 odt_en variable
394 in the [dram] section. When bit 31 of the odt_en variable is set
395 then the correction is negative. Usually the value for this is 0.
399 default 1008000000 if MACH_SUN4I
400 default 1008000000 if MACH_SUN5I
401 default 1008000000 if MACH_SUN6I
402 default 912000000 if MACH_SUN7I
403 default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
404 default 1008000000 if MACH_SUN8I
405 default 1008000000 if MACH_SUN9I
407 config SYS_CONFIG_NAME
408 default "sun4i" if MACH_SUN4I
409 default "sun5i" if MACH_SUN5I
410 default "sun6i" if MACH_SUN6I
411 default "sun7i" if MACH_SUN7I
412 default "sun8i" if MACH_SUN8I
413 default "sun9i" if MACH_SUN9I
414 default "sun50i" if MACH_SUN50I
423 bool "UART0 on MicroSD breakout board"
426 Repurpose the SD card slot for getting access to the UART0 serial
427 console. Primarily useful only for low level u-boot debugging on
428 tablets, where normal UART0 is difficult to access and requires
429 device disassembly and/or soldering. As the SD card can't be used
430 at the same time, the system can be only booted in the FEL mode.
431 Only enable this if you really know what you are doing.
433 config OLD_SUNXI_KERNEL_COMPAT
434 bool "Enable workarounds for booting old kernels"
437 Set this to enable various workarounds for old kernels, this results in
438 sub-optimal settings for newer kernels, only enable if needed.
441 string "MAC power pin"
444 Set the pin used to power the MAC. This takes a string in the format
445 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
448 string "Card detect pin for mmc0"
449 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
452 Set the card detect pin for mmc0, leave empty to not use cd. This
453 takes a string in the format understood by sunxi_name_to_gpio, e.g.
454 PH1 for pin 1 of port H.
457 string "Card detect pin for mmc1"
460 See MMC0_CD_PIN help text.
463 string "Card detect pin for mmc2"
466 See MMC0_CD_PIN help text.
469 string "Card detect pin for mmc3"
472 See MMC0_CD_PIN help text.
475 string "Pins for mmc1"
478 Set the pins used for mmc1, when applicable. This takes a string in the
479 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
482 string "Pins for mmc2"
485 See MMC1_PINS help text.
488 string "Pins for mmc3"
491 See MMC1_PINS help text.
493 config MMC_SUNXI_SLOT_EXTRA
494 int "mmc extra slot number"
497 sunxi builds always enable mmc0, some boards also have a second sdcard
498 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
501 config INITIAL_USB_SCAN_DELAY
502 int "delay initial usb scan by x ms to allow builtin devices to init"
505 Some boards have on board usb devices which need longer than the
506 USB spec's 1 second to connect from board powerup. Set this config
507 option to a non 0 value to add an extra delay before the first usb
511 string "Vbus enable pin for usb0 (otg)"
514 Set the Vbus enable pin for usb0 (otg). This takes a string in the
515 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
518 string "Vbus detect pin for usb0 (otg)"
521 Set the Vbus detect pin for usb0 (otg). This takes a string in the
522 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
525 string "ID detect pin for usb0 (otg)"
528 Set the ID detect pin for usb0 (otg). This takes a string in the
529 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
532 string "Vbus enable pin for usb1 (ehci0)"
533 default "PH6" if MACH_SUN4I || MACH_SUN7I
534 default "PH27" if MACH_SUN6I
536 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
537 a string in the format understood by sunxi_name_to_gpio, e.g.
538 PH1 for pin 1 of port H.
541 string "Vbus enable pin for usb2 (ehci1)"
542 default "PH3" if MACH_SUN4I || MACH_SUN7I
543 default "PH24" if MACH_SUN6I
545 See USB1_VBUS_PIN help text.
548 string "Vbus enable pin for usb3 (ehci2)"
551 See USB1_VBUS_PIN help text.
554 bool "Enable I2C/TWI controller 0"
555 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
556 default n if MACH_SUN6I || MACH_SUN8I
559 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
560 its clock and setting up the bus. This is especially useful on devices
561 with slaves connected to the bus or with pins exposed through e.g. an
562 expansion port/header.
565 bool "Enable I2C/TWI controller 1"
569 See I2C0_ENABLE help text.
572 bool "Enable I2C/TWI controller 2"
576 See I2C0_ENABLE help text.
578 if MACH_SUN6I || MACH_SUN7I
580 bool "Enable I2C/TWI controller 3"
584 See I2C0_ENABLE help text.
589 bool "Enable the PRCM I2C/TWI controller"
590 # This is used for the pmic on H3
591 default y if SY8106A_POWER
594 Set this to y to enable the I2C controller which is part of the PRCM.
599 bool "Enable I2C/TWI controller 4"
603 See I2C0_ENABLE help text.
607 bool "Enable support for gpio-s on axp PMICs"
610 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
613 bool "Enable graphical uboot console on HDMI, LCD or VGA"
614 depends on !MACH_SUN8I_A83T
615 depends on !MACH_SUNXI_H3_H5
616 depends on !MACH_SUN8I_R40
617 depends on !MACH_SUN8I_V3S
618 depends on !MACH_SUN9I
619 depends on !MACH_SUN50I
621 imply VIDEO_DT_SIMPLEFB
624 Say Y here to add support for using a cfb console on the HDMI, LCD
625 or VGA output found on most sunxi devices. See doc/README.video for
626 info on how to select the video output and mode.
629 bool "HDMI output support"
630 depends on VIDEO_SUNXI && !MACH_SUN8I
633 Say Y here to add support for outputting video over HDMI.
636 bool "VGA output support"
637 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
640 Say Y here to add support for outputting video over VGA.
642 config VIDEO_VGA_VIA_LCD
643 bool "VGA via LCD controller support"
644 depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
647 Say Y here to add support for external DACs connected to the parallel
648 LCD interface driving a VGA connector, such as found on the
651 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
652 bool "Force sync active high for VGA via LCD controller support"
653 depends on VIDEO_VGA_VIA_LCD
656 Say Y here if you've a board which uses opendrain drivers for the vga
657 hsync and vsync signals. Opendrain drivers cannot generate steep enough
658 positive edges for a stable video output, so on boards with opendrain
659 drivers the sync signals must always be active high.
661 config VIDEO_VGA_EXTERNAL_DAC_EN
662 string "LCD panel power enable pin"
663 depends on VIDEO_VGA_VIA_LCD
666 Set the enable pin for the external VGA DAC. This takes a string in the
667 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
669 config VIDEO_COMPOSITE
670 bool "Composite video output support"
671 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
674 Say Y here to add support for outputting composite video.
676 config VIDEO_LCD_MODE
677 string "LCD panel timing details"
678 depends on VIDEO_SUNXI
681 LCD panel timing details string, leave empty if there is no LCD panel.
682 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
683 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
684 Also see: http://linux-sunxi.org/LCD
686 config VIDEO_LCD_DCLK_PHASE
687 int "LCD panel display clock phase"
688 depends on VIDEO_SUNXI || DM_VIDEO
691 Select LCD panel display clock phase shift, range 0-3.
693 config VIDEO_LCD_POWER
694 string "LCD panel power enable pin"
695 depends on VIDEO_SUNXI
698 Set the power enable pin for the LCD panel. This takes a string in the
699 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
701 config VIDEO_LCD_RESET
702 string "LCD panel reset pin"
703 depends on VIDEO_SUNXI
706 Set the reset pin for the LCD panel. This takes a string in the format
707 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
709 config VIDEO_LCD_BL_EN
710 string "LCD panel backlight enable pin"
711 depends on VIDEO_SUNXI
714 Set the backlight enable pin for the LCD panel. This takes a string in the
715 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
718 config VIDEO_LCD_BL_PWM
719 string "LCD panel backlight pwm pin"
720 depends on VIDEO_SUNXI
723 Set the backlight pwm pin for the LCD panel. This takes a string in the
724 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
726 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
727 bool "LCD panel backlight pwm is inverted"
728 depends on VIDEO_SUNXI
731 Set this if the backlight pwm output is active low.
733 config VIDEO_LCD_PANEL_I2C
734 bool "LCD panel needs to be configured via i2c"
735 depends on VIDEO_SUNXI
739 Say y here if the LCD panel needs to be configured via i2c. This
740 will add a bitbang i2c controller using gpios to talk to the LCD.
742 config VIDEO_LCD_PANEL_I2C_SDA
743 string "LCD panel i2c interface SDA pin"
744 depends on VIDEO_LCD_PANEL_I2C
747 Set the SDA pin for the LCD i2c interface. This takes a string in the
748 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
750 config VIDEO_LCD_PANEL_I2C_SCL
751 string "LCD panel i2c interface SCL pin"
752 depends on VIDEO_LCD_PANEL_I2C
755 Set the SCL pin for the LCD i2c interface. This takes a string in the
756 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
759 # Note only one of these may be selected at a time! But hidden choices are
760 # not supported by Kconfig
761 config VIDEO_LCD_IF_PARALLEL
764 config VIDEO_LCD_IF_LVDS
772 bool "Display Engine 2 video driver"
776 imply VIDEO_DT_SIMPLEFB
779 Say y here if you want to build DE2 video driver which is present on
780 newer SoCs. Currently only HDMI output is supported.
784 prompt "LCD panel support"
785 depends on VIDEO_SUNXI
787 Select which type of LCD panel to support.
789 config VIDEO_LCD_PANEL_PARALLEL
790 bool "Generic parallel interface LCD panel"
791 select VIDEO_LCD_IF_PARALLEL
793 config VIDEO_LCD_PANEL_LVDS
794 bool "Generic lvds interface LCD panel"
795 select VIDEO_LCD_IF_LVDS
797 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
798 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
799 select VIDEO_LCD_SSD2828
800 select VIDEO_LCD_IF_PARALLEL
802 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
804 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
805 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
806 select VIDEO_LCD_ANX9804
807 select VIDEO_LCD_IF_PARALLEL
808 select VIDEO_LCD_PANEL_I2C
810 Select this for eDP LCD panels with 4 lanes running at 1.62G,
811 connected via an ANX9804 bridge chip.
813 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
814 bool "Hitachi tx18d42vm LCD panel"
815 select VIDEO_LCD_HITACHI_TX18D42VM
816 select VIDEO_LCD_IF_LVDS
818 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
820 config VIDEO_LCD_TL059WV5C0
821 bool "tl059wv5c0 LCD panel"
822 select VIDEO_LCD_PANEL_I2C
823 select VIDEO_LCD_IF_PARALLEL
825 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
826 Aigo M60/M608/M606 tablets.
831 string "SATA power pin"
834 Set the pins used to power the SATA. This takes a string in the
835 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
839 int "GMAC Transmit Clock Delay Chain"
842 Set the GMAC Transmit Clock Delay Chain value.
844 config SPL_STACK_R_ADDR
845 default 0x4fe00000 if MACH_SUN4I
846 default 0x4fe00000 if MACH_SUN5I
847 default 0x4fe00000 if MACH_SUN6I
848 default 0x4fe00000 if MACH_SUN7I
849 default 0x4fe00000 if MACH_SUN8I
850 default 0x2fe00000 if MACH_SUN9I
851 default 0x4fe00000 if MACH_SUN50I
854 bool "Support for SPI Flash on Allwinner SoCs in SPL"
855 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
857 Enable support for SPI Flash. This option allows SPL to read from
858 sunxi SPI Flash. It uses the same method as the boot ROM, so does
859 not need any extra configuration.