4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
7 default " Allwinner Technology"
10 bool "Allwinner sun6i internal P2WI controller"
12 If you say yes to this option, support will be included for the
13 P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi
15 The P2WI looks like an SMBus controller (which supports only byte
16 accesses), except that it only supports one slave device.
17 This interface is used to connect to specific PMIC devices (like the
23 Support for the PRCM (Power/Reset/Clock Management) unit available
27 bool "Sunxi AXP PMIC bus access helpers"
29 Select this PMIC bus access helpers for Sunxi platform PRCM or other
30 AXP family PMIC devices.
33 bool "Allwinner sunXi Reduced Serial Bus Driver"
35 Say y here to enable support for Allwinner's Reduced Serial Bus
36 (RSB) support. This controller is responsible for communicating
37 with various RSB based devices, such as AXP223, AXP8XX PMICs,
40 config SUNXI_HIGH_SRAM
44 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
45 with the first SRAM region being located at address 0.
46 Some newer SoCs map the boot ROM at address 0 instead and move the
47 SRAM to 64KB, just behind the mask ROM.
48 Chips using the latter setup are supposed to select this option to
49 adjust the addresses accordingly.
51 # Note only one of these may be selected at a time! But hidden choices are
52 # not supported by Kconfig
53 config SUNXI_GEN_SUN4I
56 Select this for sunxi SoCs which have resets and clocks set up
57 as the original A10 (mach-sun4i).
59 config SUNXI_GEN_SUN6I
62 Select this for sunxi SoCs which have sun6i like periphery, like
63 separate ahb reset control registers, custom pmic bus, new style
69 Select this for sunxi SoCs which uses a DRAM controller like the
70 DesignWare controller used in H3, mainly SoCs after H3, which do
71 not have official open-source DRAM initialization code, but can
72 use modified H3 DRAM initialization code.
75 config SUNXI_DRAM_DW_16BIT
78 Select this for sunxi SoCs with DesignWare DRAM controller and
79 have only 16-bit memory buswidth.
81 config SUNXI_DRAM_DW_32BIT
84 Select this for sunxi SoCs with DesignWare DRAM controller with
85 32-bit memory buswidth.
88 config MACH_SUNXI_H3_H5
93 select SUNXI_DRAM_DW_32BIT
94 select SUNXI_GEN_SUN6I
98 prompt "Sunxi SoC Variant"
102 bool "sun4i (Allwinner A10)"
104 select ARM_CORTEX_CPU_IS_UP
105 select SUNXI_GEN_SUN4I
109 bool "sun5i (Allwinner A13)"
111 select ARM_CORTEX_CPU_IS_UP
112 select SUNXI_GEN_SUN4I
114 imply CONS_INDEX_2 if !DM_SERIAL
117 bool "sun6i (Allwinner A31)"
119 select CPU_V7_HAS_NONSEC
120 select CPU_V7_HAS_VIRT
121 select ARCH_SUPPORT_PSCI
124 select SUNXI_GEN_SUN6I
126 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
129 bool "sun7i (Allwinner A20)"
131 select CPU_V7_HAS_NONSEC
132 select CPU_V7_HAS_VIRT
133 select ARCH_SUPPORT_PSCI
134 select SUNXI_GEN_SUN4I
136 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
138 config MACH_SUN8I_A23
139 bool "sun8i (Allwinner A23)"
141 select CPU_V7_HAS_NONSEC
142 select CPU_V7_HAS_VIRT
143 select ARCH_SUPPORT_PSCI
144 select SUNXI_GEN_SUN6I
146 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
147 imply CONS_INDEX_5 if !DM_SERIAL
149 config MACH_SUN8I_A33
150 bool "sun8i (Allwinner A33)"
152 select CPU_V7_HAS_NONSEC
153 select CPU_V7_HAS_VIRT
154 select ARCH_SUPPORT_PSCI
155 select SUNXI_GEN_SUN6I
157 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
158 imply CONS_INDEX_5 if !DM_SERIAL
160 config MACH_SUN8I_A83T
161 bool "sun8i (Allwinner A83T)"
163 select SUNXI_GEN_SUN6I
164 select MMC_SUNXI_HAS_NEW_MODE
168 bool "sun8i (Allwinner H3)"
170 select CPU_V7_HAS_NONSEC
171 select CPU_V7_HAS_VIRT
172 select ARCH_SUPPORT_PSCI
173 select MACH_SUNXI_H3_H5
174 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
176 config MACH_SUN8I_R40
177 bool "sun8i (Allwinner R40)"
179 select CPU_V7_HAS_NONSEC
180 select CPU_V7_HAS_VIRT
181 select ARCH_SUPPORT_PSCI
182 select SUNXI_GEN_SUN6I
185 select SUNXI_DRAM_DW_32BIT
187 config MACH_SUN8I_V3S
188 bool "sun8i (Allwinner V3s)"
190 select CPU_V7_HAS_NONSEC
191 select CPU_V7_HAS_VIRT
192 select ARCH_SUPPORT_PSCI
193 select SUNXI_GEN_SUN6I
195 select SUNXI_DRAM_DW_16BIT
197 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
200 bool "sun9i (Allwinner A80)"
203 select SUNXI_HIGH_SRAM
204 select SUNXI_GEN_SUN6I
209 bool "sun50i (Allwinner A64)"
213 select SUNXI_GEN_SUN6I
214 select SUNXI_HIGH_SRAM
217 select SUNXI_DRAM_DW_32BIT
221 config MACH_SUN50I_H5
222 bool "sun50i (Allwinner H5)"
224 select MACH_SUNXI_H3_H5
225 select SUNXI_HIGH_SRAM
231 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
236 default y if MACH_SUN8I_A23
237 default y if MACH_SUN8I_A33
238 default y if MACH_SUN8I_A83T
239 default y if MACH_SUNXI_H3_H5
240 default y if MACH_SUN8I_R40
241 default y if MACH_SUN8I_V3S
243 config RESERVE_ALLWINNER_BOOT0_HEADER
244 bool "reserve space for Allwinner boot0 header"
245 select ENABLE_ARM_SOC_BOOT0_HOOK
247 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
248 filled with magic values post build. The Allwinner provided boot0
249 blob relies on this information to load and execute U-Boot.
250 Only needed on 64-bit Allwinner boards so far when using boot0.
252 config ARM_BOOT_HOOK_RMR
256 select ENABLE_ARM_SOC_BOOT0_HOOK
258 Insert some ARM32 code at the very beginning of the U-Boot binary
259 which uses an RMR register write to bring the core into AArch64 mode.
260 The very first instruction acts as a switch, since it's carefully
261 chosen to be a NOP in one mode and a branch in the other, so the
262 code would only be executed if not already in AArch64.
263 This allows both the SPL and the U-Boot proper to be entered in
264 either mode and switch to AArch64 if needed.
267 config SUNXI_DRAM_DDR3
270 config SUNXI_DRAM_DDR2
273 config SUNXI_DRAM_LPDDR3
277 prompt "DRAM Type and Timing"
278 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
279 default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
281 config SUNXI_DRAM_DDR3_1333
283 select SUNXI_DRAM_DDR3
284 depends on !MACH_SUN8I_V3S
286 This option is the original only supported memory type, which suits
287 many H3/H5/A64 boards available now.
289 config SUNXI_DRAM_LPDDR3_STOCK
290 bool "LPDDR3 with Allwinner stock configuration"
291 select SUNXI_DRAM_LPDDR3
293 This option is the LPDDR3 timing used by the stock boot0 by
296 config SUNXI_DRAM_DDR2_V3S
297 bool "DDR2 found in V3s chip"
298 select SUNXI_DRAM_DDR2
299 depends on MACH_SUN8I_V3S
301 This option is only for the DDR2 memory chip which is co-packaged in
308 int "sunxi dram type"
309 depends on MACH_SUN8I_A83T
312 Set the dram type, 3: DDR3, 7: LPDDR3
315 int "sunxi dram clock speed"
316 default 792 if MACH_SUN9I
317 default 648 if MACH_SUN8I_R40
318 default 312 if MACH_SUN6I || MACH_SUN8I
319 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
321 default 672 if MACH_SUN50I
323 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
324 must be a multiple of 24. For the sun9i (A80), the tested values
325 (for DDR3-1600) are 312 to 792.
327 if MACH_SUN5I || MACH_SUN7I
329 int "sunxi mbus clock speed"
332 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
337 int "sunxi dram zq value"
338 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
339 default 127 if MACH_SUN7I
340 default 14779 if MACH_SUN8I_V3S
341 default 3881979 if MACH_SUN8I_R40
342 default 4145117 if MACH_SUN9I
343 default 3881915 if MACH_SUN50I
345 Set the dram zq value.
348 bool "sunxi dram odt enable"
349 default n if !MACH_SUN8I_A23
350 default y if MACH_SUN8I_A23
351 default y if MACH_SUN8I_R40
352 default y if MACH_SUN50I
354 Select this to enable dram odt (on die termination).
356 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
358 int "sunxi dram emr1 value"
359 default 0 if MACH_SUN4I
360 default 4 if MACH_SUN5I || MACH_SUN7I
362 Set the dram controller emr1 value.
365 hex "sunxi dram tpr3 value"
368 Set the dram controller tpr3 parameter. This parameter configures
369 the delay on the command lane and also phase shifts, which are
370 applied for sampling incoming read data. The default value 0
371 means that no phase/delay adjustments are necessary. Properly
372 configuring this parameter increases reliability at high DRAM
375 config DRAM_DQS_GATING_DELAY
376 hex "sunxi dram dqs_gating_delay value"
379 Set the dram controller dqs_gating_delay parmeter. Each byte
380 encodes the DQS gating delay for each byte lane. The delay
381 granularity is 1/4 cycle. For example, the value 0x05060606
382 means that the delay is 5 quarter-cycles for one lane (1.25
383 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
384 The default value 0 means autodetection. The results of hardware
385 autodetection are not very reliable and depend on the chip
386 temperature (sometimes producing different results on cold start
387 and warm reboot). But the accuracy of hardware autodetection
388 is usually good enough, unless running at really high DRAM
389 clocks speeds (up to 600MHz). If unsure, keep as 0.
392 prompt "sunxi dram timings"
393 default DRAM_TIMINGS_VENDOR_MAGIC
395 Select the timings of the DDR3 chips.
397 config DRAM_TIMINGS_VENDOR_MAGIC
398 bool "Magic vendor timings from Android"
400 The same DRAM timings as in the Allwinner boot0 bootloader.
402 config DRAM_TIMINGS_DDR3_1066F_1333H
403 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
405 Use the timings of the standard JEDEC DDR3-1066F speed bin for
406 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
407 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
408 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
409 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
410 that down binning to DDR3-1066F is supported (because DDR3-1066F
411 uses a bit faster timings than DDR3-1333H).
413 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
414 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
416 Use the timings of the slowest possible JEDEC speed bin for the
417 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
418 DDR3-800E, DDR3-1066G or DDR3-1333J.
425 config DRAM_ODT_CORRECTION
426 int "sunxi dram odt correction value"
429 Set the dram odt correction value (range -255 - 255). In allwinner
430 fex files, this option is found in bits 8-15 of the u32 odt_en variable
431 in the [dram] section. When bit 31 of the odt_en variable is set
432 then the correction is negative. Usually the value for this is 0.
436 default 1008000000 if MACH_SUN4I
437 default 1008000000 if MACH_SUN5I
438 default 1008000000 if MACH_SUN6I
439 default 912000000 if MACH_SUN7I
440 default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
441 default 1008000000 if MACH_SUN8I
442 default 1008000000 if MACH_SUN9I
444 config SYS_CONFIG_NAME
445 default "sun4i" if MACH_SUN4I
446 default "sun5i" if MACH_SUN5I
447 default "sun6i" if MACH_SUN6I
448 default "sun7i" if MACH_SUN7I
449 default "sun8i" if MACH_SUN8I
450 default "sun9i" if MACH_SUN9I
451 default "sun50i" if MACH_SUN50I
460 bool "UART0 on MicroSD breakout board"
463 Repurpose the SD card slot for getting access to the UART0 serial
464 console. Primarily useful only for low level u-boot debugging on
465 tablets, where normal UART0 is difficult to access and requires
466 device disassembly and/or soldering. As the SD card can't be used
467 at the same time, the system can be only booted in the FEL mode.
468 Only enable this if you really know what you are doing.
470 config OLD_SUNXI_KERNEL_COMPAT
471 bool "Enable workarounds for booting old kernels"
474 Set this to enable various workarounds for old kernels, this results in
475 sub-optimal settings for newer kernels, only enable if needed.
478 string "MAC power pin"
481 Set the pin used to power the MAC. This takes a string in the format
482 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
485 string "Card detect pin for mmc0"
486 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
489 Set the card detect pin for mmc0, leave empty to not use cd. This
490 takes a string in the format understood by sunxi_name_to_gpio, e.g.
491 PH1 for pin 1 of port H.
494 string "Card detect pin for mmc1"
497 See MMC0_CD_PIN help text.
500 string "Card detect pin for mmc2"
503 See MMC0_CD_PIN help text.
506 string "Card detect pin for mmc3"
509 See MMC0_CD_PIN help text.
512 string "Pins for mmc1"
515 Set the pins used for mmc1, when applicable. This takes a string in the
516 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
519 string "Pins for mmc2"
522 See MMC1_PINS help text.
525 string "Pins for mmc3"
528 See MMC1_PINS help text.
530 config MMC_SUNXI_SLOT_EXTRA
531 int "mmc extra slot number"
534 sunxi builds always enable mmc0, some boards also have a second sdcard
535 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
538 config INITIAL_USB_SCAN_DELAY
539 int "delay initial usb scan by x ms to allow builtin devices to init"
542 Some boards have on board usb devices which need longer than the
543 USB spec's 1 second to connect from board powerup. Set this config
544 option to a non 0 value to add an extra delay before the first usb
548 string "Vbus enable pin for usb0 (otg)"
551 Set the Vbus enable pin for usb0 (otg). This takes a string in the
552 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
555 string "Vbus detect pin for usb0 (otg)"
558 Set the Vbus detect pin for usb0 (otg). This takes a string in the
559 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
562 string "ID detect pin for usb0 (otg)"
565 Set the ID detect pin for usb0 (otg). This takes a string in the
566 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
569 string "Vbus enable pin for usb1 (ehci0)"
570 default "PH6" if MACH_SUN4I || MACH_SUN7I
571 default "PH27" if MACH_SUN6I
573 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
574 a string in the format understood by sunxi_name_to_gpio, e.g.
575 PH1 for pin 1 of port H.
578 string "Vbus enable pin for usb2 (ehci1)"
579 default "PH3" if MACH_SUN4I || MACH_SUN7I
580 default "PH24" if MACH_SUN6I
582 See USB1_VBUS_PIN help text.
585 string "Vbus enable pin for usb3 (ehci2)"
588 See USB1_VBUS_PIN help text.
591 bool "Enable I2C/TWI controller 0"
592 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
593 default n if MACH_SUN6I || MACH_SUN8I
596 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
597 its clock and setting up the bus. This is especially useful on devices
598 with slaves connected to the bus or with pins exposed through e.g. an
599 expansion port/header.
602 bool "Enable I2C/TWI controller 1"
606 See I2C0_ENABLE help text.
609 bool "Enable I2C/TWI controller 2"
613 See I2C0_ENABLE help text.
615 if MACH_SUN6I || MACH_SUN7I
617 bool "Enable I2C/TWI controller 3"
621 See I2C0_ENABLE help text.
626 bool "Enable the PRCM I2C/TWI controller"
627 # This is used for the pmic on H3
628 default y if SY8106A_POWER
631 Set this to y to enable the I2C controller which is part of the PRCM.
636 bool "Enable I2C/TWI controller 4"
640 See I2C0_ENABLE help text.
644 bool "Enable support for gpio-s on axp PMICs"
647 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
650 bool "Enable graphical uboot console on HDMI, LCD or VGA"
651 depends on !MACH_SUN8I_A83T
652 depends on !MACH_SUNXI_H3_H5
653 depends on !MACH_SUN8I_R40
654 depends on !MACH_SUN8I_V3S
655 depends on !MACH_SUN9I
656 depends on !MACH_SUN50I
658 imply VIDEO_DT_SIMPLEFB
661 Say Y here to add support for using a cfb console on the HDMI, LCD
662 or VGA output found on most sunxi devices. See doc/README.video for
663 info on how to select the video output and mode.
666 bool "HDMI output support"
667 depends on VIDEO_SUNXI && !MACH_SUN8I
670 Say Y here to add support for outputting video over HDMI.
673 bool "VGA output support"
674 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
677 Say Y here to add support for outputting video over VGA.
679 config VIDEO_VGA_VIA_LCD
680 bool "VGA via LCD controller support"
681 depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
684 Say Y here to add support for external DACs connected to the parallel
685 LCD interface driving a VGA connector, such as found on the
688 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
689 bool "Force sync active high for VGA via LCD controller support"
690 depends on VIDEO_VGA_VIA_LCD
693 Say Y here if you've a board which uses opendrain drivers for the vga
694 hsync and vsync signals. Opendrain drivers cannot generate steep enough
695 positive edges for a stable video output, so on boards with opendrain
696 drivers the sync signals must always be active high.
698 config VIDEO_VGA_EXTERNAL_DAC_EN
699 string "LCD panel power enable pin"
700 depends on VIDEO_VGA_VIA_LCD
703 Set the enable pin for the external VGA DAC. This takes a string in the
704 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
706 config VIDEO_COMPOSITE
707 bool "Composite video output support"
708 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
711 Say Y here to add support for outputting composite video.
713 config VIDEO_LCD_MODE
714 string "LCD panel timing details"
715 depends on VIDEO_SUNXI
718 LCD panel timing details string, leave empty if there is no LCD panel.
719 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
720 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
721 Also see: http://linux-sunxi.org/LCD
723 config VIDEO_LCD_DCLK_PHASE
724 int "LCD panel display clock phase"
725 depends on VIDEO_SUNXI || DM_VIDEO
728 Select LCD panel display clock phase shift, range 0-3.
730 config VIDEO_LCD_POWER
731 string "LCD panel power enable pin"
732 depends on VIDEO_SUNXI
735 Set the power enable pin for the LCD panel. This takes a string in the
736 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
738 config VIDEO_LCD_RESET
739 string "LCD panel reset pin"
740 depends on VIDEO_SUNXI
743 Set the reset pin for the LCD panel. This takes a string in the format
744 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
746 config VIDEO_LCD_BL_EN
747 string "LCD panel backlight enable pin"
748 depends on VIDEO_SUNXI
751 Set the backlight enable pin for the LCD panel. This takes a string in the
752 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
755 config VIDEO_LCD_BL_PWM
756 string "LCD panel backlight pwm pin"
757 depends on VIDEO_SUNXI
760 Set the backlight pwm pin for the LCD panel. This takes a string in the
761 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
763 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
764 bool "LCD panel backlight pwm is inverted"
765 depends on VIDEO_SUNXI
768 Set this if the backlight pwm output is active low.
770 config VIDEO_LCD_PANEL_I2C
771 bool "LCD panel needs to be configured via i2c"
772 depends on VIDEO_SUNXI
776 Say y here if the LCD panel needs to be configured via i2c. This
777 will add a bitbang i2c controller using gpios to talk to the LCD.
779 config VIDEO_LCD_PANEL_I2C_SDA
780 string "LCD panel i2c interface SDA pin"
781 depends on VIDEO_LCD_PANEL_I2C
784 Set the SDA pin for the LCD i2c interface. This takes a string in the
785 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
787 config VIDEO_LCD_PANEL_I2C_SCL
788 string "LCD panel i2c interface SCL pin"
789 depends on VIDEO_LCD_PANEL_I2C
792 Set the SCL pin for the LCD i2c interface. This takes a string in the
793 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
796 # Note only one of these may be selected at a time! But hidden choices are
797 # not supported by Kconfig
798 config VIDEO_LCD_IF_PARALLEL
801 config VIDEO_LCD_IF_LVDS
809 bool "Display Engine 2 video driver"
813 imply VIDEO_DT_SIMPLEFB
816 Say y here if you want to build DE2 video driver which is present on
817 newer SoCs. Currently only HDMI output is supported.
821 prompt "LCD panel support"
822 depends on VIDEO_SUNXI
824 Select which type of LCD panel to support.
826 config VIDEO_LCD_PANEL_PARALLEL
827 bool "Generic parallel interface LCD panel"
828 select VIDEO_LCD_IF_PARALLEL
830 config VIDEO_LCD_PANEL_LVDS
831 bool "Generic lvds interface LCD panel"
832 select VIDEO_LCD_IF_LVDS
834 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
835 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
836 select VIDEO_LCD_SSD2828
837 select VIDEO_LCD_IF_PARALLEL
839 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
841 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
842 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
843 select VIDEO_LCD_ANX9804
844 select VIDEO_LCD_IF_PARALLEL
845 select VIDEO_LCD_PANEL_I2C
847 Select this for eDP LCD panels with 4 lanes running at 1.62G,
848 connected via an ANX9804 bridge chip.
850 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
851 bool "Hitachi tx18d42vm LCD panel"
852 select VIDEO_LCD_HITACHI_TX18D42VM
853 select VIDEO_LCD_IF_LVDS
855 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
857 config VIDEO_LCD_TL059WV5C0
858 bool "tl059wv5c0 LCD panel"
859 select VIDEO_LCD_PANEL_I2C
860 select VIDEO_LCD_IF_PARALLEL
862 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
863 Aigo M60/M608/M606 tablets.
868 string "SATA power pin"
871 Set the pins used to power the SATA. This takes a string in the
872 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
876 int "GMAC Transmit Clock Delay Chain"
879 Set the GMAC Transmit Clock Delay Chain value.
881 config SPL_STACK_R_ADDR
882 default 0x4fe00000 if MACH_SUN4I
883 default 0x4fe00000 if MACH_SUN5I
884 default 0x4fe00000 if MACH_SUN6I
885 default 0x4fe00000 if MACH_SUN7I
886 default 0x4fe00000 if MACH_SUN8I
887 default 0x2fe00000 if MACH_SUN9I
888 default 0x4fe00000 if MACH_SUN50I
891 bool "Support for SPI Flash on Allwinner SoCs in SPL"
892 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
894 Enable support for SPI Flash. This option allows SPL to read from
895 sunxi SPI Flash. It uses the same method as the boot ROM, so does
896 not need any extra configuration.