4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
7 default " Allwinner Technology"
12 Select this dram controller driver for Sun4/5/7i platforms,
18 Select this dram controller driver for Sun6i platforms,
24 Select this dram controller driver for Sun8i platforms,
30 Select this dram controller driver for Sun8i platforms,
36 Select this dram controller driver for Sun9i platforms,
40 bool "Allwinner sun6i internal P2WI controller"
42 If you say yes to this option, support will be included for the
43 P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi
45 The P2WI looks like an SMBus controller (which supports only byte
46 accesses), except that it only supports one slave device.
47 This interface is used to connect to specific PMIC devices (like the
53 Support for the PRCM (Power/Reset/Clock Management) unit available
57 bool "Sunxi AXP PMIC bus access helpers"
59 Select this PMIC bus access helpers for Sunxi platform PRCM or other
60 AXP family PMIC devices.
63 bool "Allwinner sunXi Reduced Serial Bus Driver"
65 Say y here to enable support for Allwinner's Reduced Serial Bus
66 (RSB) support. This controller is responsible for communicating
67 with various RSB based devices, such as AXP223, AXP8XX PMICs,
70 config SUNXI_HIGH_SRAM
74 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
75 with the first SRAM region being located at address 0.
76 Some newer SoCs map the boot ROM at address 0 instead and move the
77 SRAM to 64KB, just behind the mask ROM.
78 Chips using the latter setup are supposed to select this option to
79 adjust the addresses accordingly.
81 # Note only one of these may be selected at a time! But hidden choices are
82 # not supported by Kconfig
83 config SUNXI_GEN_SUN4I
86 Select this for sunxi SoCs which have resets and clocks set up
87 as the original A10 (mach-sun4i).
89 config SUNXI_GEN_SUN6I
92 Select this for sunxi SoCs which have sun6i like periphery, like
93 separate ahb reset control registers, custom pmic bus, new style
99 Select this for sunxi SoCs which uses a DRAM controller like the
100 DesignWare controller used in H3, mainly SoCs after H3, which do
101 not have official open-source DRAM initialization code, but can
102 use modified H3 DRAM initialization code.
105 config SUNXI_DRAM_DW_16BIT
108 Select this for sunxi SoCs with DesignWare DRAM controller and
109 have only 16-bit memory buswidth.
111 config SUNXI_DRAM_DW_32BIT
114 Select this for sunxi SoCs with DesignWare DRAM controller with
115 32-bit memory buswidth.
118 config MACH_SUNXI_H3_H5
123 select SUNXI_DRAM_DW_32BIT
124 select SUNXI_GEN_SUN6I
128 prompt "Sunxi SoC Variant"
132 bool "sun4i (Allwinner A10)"
134 select ARM_CORTEX_CPU_IS_UP
136 select SUNXI_GEN_SUN4I
140 bool "sun5i (Allwinner A13)"
142 select ARM_CORTEX_CPU_IS_UP
144 select SUNXI_GEN_SUN4I
146 imply CONS_INDEX_2 if !DM_SERIAL
149 bool "sun6i (Allwinner A31)"
151 select CPU_V7_HAS_NONSEC
152 select CPU_V7_HAS_VIRT
153 select ARCH_SUPPORT_PSCI
157 select SUNXI_GEN_SUN6I
159 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
162 bool "sun7i (Allwinner A20)"
164 select CPU_V7_HAS_NONSEC
165 select CPU_V7_HAS_VIRT
166 select ARCH_SUPPORT_PSCI
168 select SUNXI_GEN_SUN4I
170 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
172 config MACH_SUN8I_A23
173 bool "sun8i (Allwinner A23)"
175 select CPU_V7_HAS_NONSEC
176 select CPU_V7_HAS_VIRT
177 select ARCH_SUPPORT_PSCI
178 select DRAM_SUN8I_A23
179 select SUNXI_GEN_SUN6I
181 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
182 imply CONS_INDEX_5 if !DM_SERIAL
184 config MACH_SUN8I_A33
185 bool "sun8i (Allwinner A33)"
187 select CPU_V7_HAS_NONSEC
188 select CPU_V7_HAS_VIRT
189 select ARCH_SUPPORT_PSCI
190 select DRAM_SUN8I_A33
191 select SUNXI_GEN_SUN6I
193 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
194 imply CONS_INDEX_5 if !DM_SERIAL
196 config MACH_SUN8I_A83T
197 bool "sun8i (Allwinner A83T)"
199 select SUNXI_GEN_SUN6I
200 select MMC_SUNXI_HAS_NEW_MODE
204 bool "sun8i (Allwinner H3)"
206 select CPU_V7_HAS_NONSEC
207 select CPU_V7_HAS_VIRT
208 select ARCH_SUPPORT_PSCI
209 select MACH_SUNXI_H3_H5
210 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
212 config MACH_SUN8I_R40
213 bool "sun8i (Allwinner R40)"
215 select CPU_V7_HAS_NONSEC
216 select CPU_V7_HAS_VIRT
217 select ARCH_SUPPORT_PSCI
218 select SUNXI_GEN_SUN6I
221 select SUNXI_DRAM_DW_32BIT
223 config MACH_SUN8I_V3S
224 bool "sun8i (Allwinner V3s)"
226 select CPU_V7_HAS_NONSEC
227 select CPU_V7_HAS_VIRT
228 select ARCH_SUPPORT_PSCI
229 select SUNXI_GEN_SUN6I
231 select SUNXI_DRAM_DW_16BIT
233 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
236 bool "sun9i (Allwinner A80)"
240 select SUNXI_HIGH_SRAM
241 select SUNXI_GEN_SUN6I
246 bool "sun50i (Allwinner A64)"
250 select SUNXI_GEN_SUN6I
251 select SUNXI_HIGH_SRAM
254 select SUNXI_DRAM_DW_32BIT
258 config MACH_SUN50I_H5
259 bool "sun50i (Allwinner H5)"
261 select MACH_SUNXI_H3_H5
262 select SUNXI_HIGH_SRAM
268 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
273 default y if MACH_SUN8I_A23
274 default y if MACH_SUN8I_A33
275 default y if MACH_SUN8I_A83T
276 default y if MACH_SUNXI_H3_H5
277 default y if MACH_SUN8I_R40
278 default y if MACH_SUN8I_V3S
280 config RESERVE_ALLWINNER_BOOT0_HEADER
281 bool "reserve space for Allwinner boot0 header"
282 select ENABLE_ARM_SOC_BOOT0_HOOK
284 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
285 filled with magic values post build. The Allwinner provided boot0
286 blob relies on this information to load and execute U-Boot.
287 Only needed on 64-bit Allwinner boards so far when using boot0.
289 config ARM_BOOT_HOOK_RMR
293 select ENABLE_ARM_SOC_BOOT0_HOOK
295 Insert some ARM32 code at the very beginning of the U-Boot binary
296 which uses an RMR register write to bring the core into AArch64 mode.
297 The very first instruction acts as a switch, since it's carefully
298 chosen to be a NOP in one mode and a branch in the other, so the
299 code would only be executed if not already in AArch64.
300 This allows both the SPL and the U-Boot proper to be entered in
301 either mode and switch to AArch64 if needed.
304 config SUNXI_DRAM_DDR3
307 config SUNXI_DRAM_DDR2
310 config SUNXI_DRAM_LPDDR3
314 prompt "DRAM Type and Timing"
315 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
316 default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
318 config SUNXI_DRAM_DDR3_1333
320 select SUNXI_DRAM_DDR3
321 depends on !MACH_SUN8I_V3S
323 This option is the original only supported memory type, which suits
324 many H3/H5/A64 boards available now.
326 config SUNXI_DRAM_LPDDR3_STOCK
327 bool "LPDDR3 with Allwinner stock configuration"
328 select SUNXI_DRAM_LPDDR3
330 This option is the LPDDR3 timing used by the stock boot0 by
333 config SUNXI_DRAM_DDR2_V3S
334 bool "DDR2 found in V3s chip"
335 select SUNXI_DRAM_DDR2
336 depends on MACH_SUN8I_V3S
338 This option is only for the DDR2 memory chip which is co-packaged in
345 int "sunxi dram type"
346 depends on MACH_SUN8I_A83T
349 Set the dram type, 3: DDR3, 7: LPDDR3
352 int "sunxi dram clock speed"
353 default 792 if MACH_SUN9I
354 default 648 if MACH_SUN8I_R40
355 default 312 if MACH_SUN6I || MACH_SUN8I
356 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
358 default 672 if MACH_SUN50I
360 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
361 must be a multiple of 24. For the sun9i (A80), the tested values
362 (for DDR3-1600) are 312 to 792.
364 if MACH_SUN5I || MACH_SUN7I
366 int "sunxi mbus clock speed"
369 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
374 int "sunxi dram zq value"
375 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
376 default 127 if MACH_SUN7I
377 default 14779 if MACH_SUN8I_V3S
378 default 3881979 if MACH_SUN8I_R40
379 default 4145117 if MACH_SUN9I
380 default 3881915 if MACH_SUN50I
382 Set the dram zq value.
385 bool "sunxi dram odt enable"
386 default n if !MACH_SUN8I_A23
387 default y if MACH_SUN8I_A23
388 default y if MACH_SUN8I_R40
389 default y if MACH_SUN50I
391 Select this to enable dram odt (on die termination).
393 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
395 int "sunxi dram emr1 value"
396 default 0 if MACH_SUN4I
397 default 4 if MACH_SUN5I || MACH_SUN7I
399 Set the dram controller emr1 value.
402 hex "sunxi dram tpr3 value"
405 Set the dram controller tpr3 parameter. This parameter configures
406 the delay on the command lane and also phase shifts, which are
407 applied for sampling incoming read data. The default value 0
408 means that no phase/delay adjustments are necessary. Properly
409 configuring this parameter increases reliability at high DRAM
412 config DRAM_DQS_GATING_DELAY
413 hex "sunxi dram dqs_gating_delay value"
416 Set the dram controller dqs_gating_delay parmeter. Each byte
417 encodes the DQS gating delay for each byte lane. The delay
418 granularity is 1/4 cycle. For example, the value 0x05060606
419 means that the delay is 5 quarter-cycles for one lane (1.25
420 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
421 The default value 0 means autodetection. The results of hardware
422 autodetection are not very reliable and depend on the chip
423 temperature (sometimes producing different results on cold start
424 and warm reboot). But the accuracy of hardware autodetection
425 is usually good enough, unless running at really high DRAM
426 clocks speeds (up to 600MHz). If unsure, keep as 0.
429 prompt "sunxi dram timings"
430 default DRAM_TIMINGS_VENDOR_MAGIC
432 Select the timings of the DDR3 chips.
434 config DRAM_TIMINGS_VENDOR_MAGIC
435 bool "Magic vendor timings from Android"
437 The same DRAM timings as in the Allwinner boot0 bootloader.
439 config DRAM_TIMINGS_DDR3_1066F_1333H
440 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
442 Use the timings of the standard JEDEC DDR3-1066F speed bin for
443 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
444 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
445 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
446 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
447 that down binning to DDR3-1066F is supported (because DDR3-1066F
448 uses a bit faster timings than DDR3-1333H).
450 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
451 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
453 Use the timings of the slowest possible JEDEC speed bin for the
454 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
455 DDR3-800E, DDR3-1066G or DDR3-1333J.
462 config DRAM_ODT_CORRECTION
463 int "sunxi dram odt correction value"
466 Set the dram odt correction value (range -255 - 255). In allwinner
467 fex files, this option is found in bits 8-15 of the u32 odt_en variable
468 in the [dram] section. When bit 31 of the odt_en variable is set
469 then the correction is negative. Usually the value for this is 0.
473 default 1008000000 if MACH_SUN4I
474 default 1008000000 if MACH_SUN5I
475 default 1008000000 if MACH_SUN6I
476 default 912000000 if MACH_SUN7I
477 default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
478 default 1008000000 if MACH_SUN8I
479 default 1008000000 if MACH_SUN9I
481 config SYS_CONFIG_NAME
482 default "sun4i" if MACH_SUN4I
483 default "sun5i" if MACH_SUN5I
484 default "sun6i" if MACH_SUN6I
485 default "sun7i" if MACH_SUN7I
486 default "sun8i" if MACH_SUN8I
487 default "sun9i" if MACH_SUN9I
488 default "sun50i" if MACH_SUN50I
497 bool "UART0 on MicroSD breakout board"
500 Repurpose the SD card slot for getting access to the UART0 serial
501 console. Primarily useful only for low level u-boot debugging on
502 tablets, where normal UART0 is difficult to access and requires
503 device disassembly and/or soldering. As the SD card can't be used
504 at the same time, the system can be only booted in the FEL mode.
505 Only enable this if you really know what you are doing.
507 config OLD_SUNXI_KERNEL_COMPAT
508 bool "Enable workarounds for booting old kernels"
511 Set this to enable various workarounds for old kernels, this results in
512 sub-optimal settings for newer kernels, only enable if needed.
515 string "MAC power pin"
518 Set the pin used to power the MAC. This takes a string in the format
519 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
522 string "Card detect pin for mmc0"
523 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
526 Set the card detect pin for mmc0, leave empty to not use cd. This
527 takes a string in the format understood by sunxi_name_to_gpio, e.g.
528 PH1 for pin 1 of port H.
531 string "Card detect pin for mmc1"
534 See MMC0_CD_PIN help text.
537 string "Card detect pin for mmc2"
540 See MMC0_CD_PIN help text.
543 string "Card detect pin for mmc3"
546 See MMC0_CD_PIN help text.
549 string "Pins for mmc1"
552 Set the pins used for mmc1, when applicable. This takes a string in the
553 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
556 string "Pins for mmc2"
559 See MMC1_PINS help text.
562 string "Pins for mmc3"
565 See MMC1_PINS help text.
567 config MMC_SUNXI_SLOT_EXTRA
568 int "mmc extra slot number"
571 sunxi builds always enable mmc0, some boards also have a second sdcard
572 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
575 config INITIAL_USB_SCAN_DELAY
576 int "delay initial usb scan by x ms to allow builtin devices to init"
579 Some boards have on board usb devices which need longer than the
580 USB spec's 1 second to connect from board powerup. Set this config
581 option to a non 0 value to add an extra delay before the first usb
585 string "Vbus enable pin for usb0 (otg)"
588 Set the Vbus enable pin for usb0 (otg). This takes a string in the
589 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
592 string "Vbus detect pin for usb0 (otg)"
595 Set the Vbus detect pin for usb0 (otg). This takes a string in the
596 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
599 string "ID detect pin for usb0 (otg)"
602 Set the ID detect pin for usb0 (otg). This takes a string in the
603 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
606 string "Vbus enable pin for usb1 (ehci0)"
607 default "PH6" if MACH_SUN4I || MACH_SUN7I
608 default "PH27" if MACH_SUN6I
610 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
611 a string in the format understood by sunxi_name_to_gpio, e.g.
612 PH1 for pin 1 of port H.
615 string "Vbus enable pin for usb2 (ehci1)"
616 default "PH3" if MACH_SUN4I || MACH_SUN7I
617 default "PH24" if MACH_SUN6I
619 See USB1_VBUS_PIN help text.
622 string "Vbus enable pin for usb3 (ehci2)"
625 See USB1_VBUS_PIN help text.
628 bool "Enable I2C/TWI controller 0"
629 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
630 default n if MACH_SUN6I || MACH_SUN8I
633 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
634 its clock and setting up the bus. This is especially useful on devices
635 with slaves connected to the bus or with pins exposed through e.g. an
636 expansion port/header.
639 bool "Enable I2C/TWI controller 1"
643 See I2C0_ENABLE help text.
646 bool "Enable I2C/TWI controller 2"
650 See I2C0_ENABLE help text.
652 if MACH_SUN6I || MACH_SUN7I
654 bool "Enable I2C/TWI controller 3"
658 See I2C0_ENABLE help text.
663 bool "Enable the PRCM I2C/TWI controller"
664 # This is used for the pmic on H3
665 default y if SY8106A_POWER
668 Set this to y to enable the I2C controller which is part of the PRCM.
673 bool "Enable I2C/TWI controller 4"
677 See I2C0_ENABLE help text.
681 bool "Enable support for gpio-s on axp PMICs"
684 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
687 bool "Enable graphical uboot console on HDMI, LCD or VGA"
688 depends on !MACH_SUN8I_A83T
689 depends on !MACH_SUNXI_H3_H5
690 depends on !MACH_SUN8I_R40
691 depends on !MACH_SUN8I_V3S
692 depends on !MACH_SUN9I
693 depends on !MACH_SUN50I
695 imply VIDEO_DT_SIMPLEFB
698 Say Y here to add support for using a cfb console on the HDMI, LCD
699 or VGA output found on most sunxi devices. See doc/README.video for
700 info on how to select the video output and mode.
703 bool "HDMI output support"
704 depends on VIDEO_SUNXI && !MACH_SUN8I
707 Say Y here to add support for outputting video over HDMI.
710 bool "VGA output support"
711 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
714 Say Y here to add support for outputting video over VGA.
716 config VIDEO_VGA_VIA_LCD
717 bool "VGA via LCD controller support"
718 depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
721 Say Y here to add support for external DACs connected to the parallel
722 LCD interface driving a VGA connector, such as found on the
725 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
726 bool "Force sync active high for VGA via LCD controller support"
727 depends on VIDEO_VGA_VIA_LCD
730 Say Y here if you've a board which uses opendrain drivers for the vga
731 hsync and vsync signals. Opendrain drivers cannot generate steep enough
732 positive edges for a stable video output, so on boards with opendrain
733 drivers the sync signals must always be active high.
735 config VIDEO_VGA_EXTERNAL_DAC_EN
736 string "LCD panel power enable pin"
737 depends on VIDEO_VGA_VIA_LCD
740 Set the enable pin for the external VGA DAC. This takes a string in the
741 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
743 config VIDEO_COMPOSITE
744 bool "Composite video output support"
745 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
748 Say Y here to add support for outputting composite video.
750 config VIDEO_LCD_MODE
751 string "LCD panel timing details"
752 depends on VIDEO_SUNXI
755 LCD panel timing details string, leave empty if there is no LCD panel.
756 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
757 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
758 Also see: http://linux-sunxi.org/LCD
760 config VIDEO_LCD_DCLK_PHASE
761 int "LCD panel display clock phase"
762 depends on VIDEO_SUNXI || DM_VIDEO
765 Select LCD panel display clock phase shift, range 0-3.
767 config VIDEO_LCD_POWER
768 string "LCD panel power enable pin"
769 depends on VIDEO_SUNXI
772 Set the power enable pin for the LCD panel. This takes a string in the
773 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
775 config VIDEO_LCD_RESET
776 string "LCD panel reset pin"
777 depends on VIDEO_SUNXI
780 Set the reset pin for the LCD panel. This takes a string in the format
781 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
783 config VIDEO_LCD_BL_EN
784 string "LCD panel backlight enable pin"
785 depends on VIDEO_SUNXI
788 Set the backlight enable pin for the LCD panel. This takes a string in the
789 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
792 config VIDEO_LCD_BL_PWM
793 string "LCD panel backlight pwm pin"
794 depends on VIDEO_SUNXI
797 Set the backlight pwm pin for the LCD panel. This takes a string in the
798 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
800 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
801 bool "LCD panel backlight pwm is inverted"
802 depends on VIDEO_SUNXI
805 Set this if the backlight pwm output is active low.
807 config VIDEO_LCD_PANEL_I2C
808 bool "LCD panel needs to be configured via i2c"
809 depends on VIDEO_SUNXI
813 Say y here if the LCD panel needs to be configured via i2c. This
814 will add a bitbang i2c controller using gpios to talk to the LCD.
816 config VIDEO_LCD_PANEL_I2C_SDA
817 string "LCD panel i2c interface SDA pin"
818 depends on VIDEO_LCD_PANEL_I2C
821 Set the SDA pin for the LCD i2c interface. This takes a string in the
822 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
824 config VIDEO_LCD_PANEL_I2C_SCL
825 string "LCD panel i2c interface SCL pin"
826 depends on VIDEO_LCD_PANEL_I2C
829 Set the SCL pin for the LCD i2c interface. This takes a string in the
830 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
833 # Note only one of these may be selected at a time! But hidden choices are
834 # not supported by Kconfig
835 config VIDEO_LCD_IF_PARALLEL
838 config VIDEO_LCD_IF_LVDS
846 bool "Display Engine 2 video driver"
850 imply VIDEO_DT_SIMPLEFB
853 Say y here if you want to build DE2 video driver which is present on
854 newer SoCs. Currently only HDMI output is supported.
858 prompt "LCD panel support"
859 depends on VIDEO_SUNXI
861 Select which type of LCD panel to support.
863 config VIDEO_LCD_PANEL_PARALLEL
864 bool "Generic parallel interface LCD panel"
865 select VIDEO_LCD_IF_PARALLEL
867 config VIDEO_LCD_PANEL_LVDS
868 bool "Generic lvds interface LCD panel"
869 select VIDEO_LCD_IF_LVDS
871 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
872 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
873 select VIDEO_LCD_SSD2828
874 select VIDEO_LCD_IF_PARALLEL
876 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
878 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
879 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
880 select VIDEO_LCD_ANX9804
881 select VIDEO_LCD_IF_PARALLEL
882 select VIDEO_LCD_PANEL_I2C
884 Select this for eDP LCD panels with 4 lanes running at 1.62G,
885 connected via an ANX9804 bridge chip.
887 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
888 bool "Hitachi tx18d42vm LCD panel"
889 select VIDEO_LCD_HITACHI_TX18D42VM
890 select VIDEO_LCD_IF_LVDS
892 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
894 config VIDEO_LCD_TL059WV5C0
895 bool "tl059wv5c0 LCD panel"
896 select VIDEO_LCD_PANEL_I2C
897 select VIDEO_LCD_IF_PARALLEL
899 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
900 Aigo M60/M608/M606 tablets.
905 string "SATA power pin"
908 Set the pins used to power the SATA. This takes a string in the
909 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
913 int "GMAC Transmit Clock Delay Chain"
916 Set the GMAC Transmit Clock Delay Chain value.
918 config SPL_STACK_R_ADDR
919 default 0x4fe00000 if MACH_SUN4I
920 default 0x4fe00000 if MACH_SUN5I
921 default 0x4fe00000 if MACH_SUN6I
922 default 0x4fe00000 if MACH_SUN7I
923 default 0x4fe00000 if MACH_SUN8I
924 default 0x2fe00000 if MACH_SUN9I
925 default 0x4fe00000 if MACH_SUN50I
928 bool "Support for SPI Flash on Allwinner SoCs in SPL"
929 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
931 Enable support for SPI Flash. This option allows SPL to read from
932 sunxi SPI Flash. It uses the same method as the boot ROM, so does
933 not need any extra configuration.