4 default " Allwinner Technology"
10 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
11 with the first SRAM region being located at address 0.
12 Some newer SoCs map the boot ROM at address 0 instead and move the
13 SRAM to 64KB, just behind the mask ROM.
14 Chips using the latter setup are supposed to select this option to
15 adjust the addresses accordingly.
17 # Note only one of these may be selected at a time! But hidden choices are
18 # not supported by Kconfig
19 config SUNXI_GEN_SUN4I
22 Select this for sunxi SoCs which have resets and clocks set up
23 as the original A10 (mach-sun4i).
25 config SUNXI_GEN_SUN6I
28 Select this for sunxi SoCs which have sun6i like periphery, like
29 separate ahb reset control registers, custom pmic bus, new style
33 config MACH_SUNXI_H3_H5
37 select SUNXI_GEN_SUN6I
41 prompt "Sunxi SoC Variant"
45 bool "sun4i (Allwinner A10)"
47 select ARM_CORTEX_CPU_IS_UP
48 select SUNXI_GEN_SUN4I
52 bool "sun5i (Allwinner A13)"
54 select ARM_CORTEX_CPU_IS_UP
55 select SUNXI_GEN_SUN4I
59 bool "sun6i (Allwinner A31)"
61 select CPU_V7_HAS_NONSEC
62 select CPU_V7_HAS_VIRT
63 select ARCH_SUPPORT_PSCI
64 select SUNXI_GEN_SUN6I
66 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
69 bool "sun7i (Allwinner A20)"
71 select CPU_V7_HAS_NONSEC
72 select CPU_V7_HAS_VIRT
73 select ARCH_SUPPORT_PSCI
74 select SUNXI_GEN_SUN4I
76 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
79 bool "sun8i (Allwinner A23)"
81 select CPU_V7_HAS_NONSEC
82 select CPU_V7_HAS_VIRT
83 select ARCH_SUPPORT_PSCI
84 select SUNXI_GEN_SUN6I
86 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
89 bool "sun8i (Allwinner A33)"
91 select CPU_V7_HAS_NONSEC
92 select CPU_V7_HAS_VIRT
93 select ARCH_SUPPORT_PSCI
94 select SUNXI_GEN_SUN6I
96 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
98 config MACH_SUN8I_A83T
99 bool "sun8i (Allwinner A83T)"
101 select SUNXI_GEN_SUN6I
105 bool "sun8i (Allwinner H3)"
107 select CPU_V7_HAS_NONSEC
108 select CPU_V7_HAS_VIRT
109 select ARCH_SUPPORT_PSCI
110 select MACH_SUNXI_H3_H5
111 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
113 config MACH_SUN8I_R40
114 bool "sun8i (Allwinner R40)"
116 select CPU_V7_HAS_NONSEC
117 select CPU_V7_HAS_VIRT
118 select ARCH_SUPPORT_PSCI
119 select SUNXI_GEN_SUN6I
122 config MACH_SUN8I_V3S
123 bool "sun8i (Allwinner V3s)"
125 select CPU_V7_HAS_NONSEC
126 select CPU_V7_HAS_VIRT
127 select ARCH_SUPPORT_PSCI
128 select SUNXI_GEN_SUN6I
129 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
132 bool "sun9i (Allwinner A80)"
134 select SUNXI_HIGH_SRAM
135 select SUNXI_GEN_SUN6I
139 bool "sun50i (Allwinner A64)"
143 select SUNXI_GEN_SUN6I
144 select SUNXI_HIGH_SRAM
149 config MACH_SUN50I_H5
150 bool "sun50i (Allwinner H5)"
152 select MACH_SUNXI_H3_H5
153 select SUNXI_HIGH_SRAM
159 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
162 default y if MACH_SUN8I_A23
163 default y if MACH_SUN8I_A33
164 default y if MACH_SUN8I_A83T
165 default y if MACH_SUNXI_H3_H5
166 default y if MACH_SUN8I_R40
167 default y if MACH_SUN8I_V3S
169 config RESERVE_ALLWINNER_BOOT0_HEADER
170 bool "reserve space for Allwinner boot0 header"
171 select ENABLE_ARM_SOC_BOOT0_HOOK
173 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
174 filled with magic values post build. The Allwinner provided boot0
175 blob relies on this information to load and execute U-Boot.
176 Only needed on 64-bit Allwinner boards so far when using boot0.
178 config ARM_BOOT_HOOK_RMR
182 select ENABLE_ARM_SOC_BOOT0_HOOK
184 Insert some ARM32 code at the very beginning of the U-Boot binary
185 which uses an RMR register write to bring the core into AArch64 mode.
186 The very first instruction acts as a switch, since it's carefully
187 chosen to be a NOP in one mode and a branch in the other, so the
188 code would only be executed if not already in AArch64.
189 This allows both the SPL and the U-Boot proper to be entered in
190 either mode and switch to AArch64 if needed.
193 int "sunxi dram type"
194 depends on MACH_SUN8I_A83T
197 Set the dram type, 3: DDR3, 7: LPDDR3
200 int "sunxi dram clock speed"
201 default 792 if MACH_SUN9I
202 default 648 if MACH_SUN8I_R40
203 default 312 if MACH_SUN6I || MACH_SUN8I
204 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
205 default 672 if MACH_SUN50I
207 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
208 must be a multiple of 24. For the sun9i (A80), the tested values
209 (for DDR3-1600) are 312 to 792.
211 if MACH_SUN5I || MACH_SUN7I
213 int "sunxi mbus clock speed"
216 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
221 int "sunxi dram zq value"
222 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
223 default 127 if MACH_SUN7I
224 default 3881979 if MACH_SUN8I_R40
225 default 4145117 if MACH_SUN9I
226 default 3881915 if MACH_SUN50I
228 Set the dram zq value.
231 bool "sunxi dram odt enable"
232 default n if !MACH_SUN8I_A23
233 default y if MACH_SUN8I_A23
234 default y if MACH_SUN8I_R40
235 default y if MACH_SUN50I
237 Select this to enable dram odt (on die termination).
239 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
241 int "sunxi dram emr1 value"
242 default 0 if MACH_SUN4I
243 default 4 if MACH_SUN5I || MACH_SUN7I
245 Set the dram controller emr1 value.
248 hex "sunxi dram tpr3 value"
251 Set the dram controller tpr3 parameter. This parameter configures
252 the delay on the command lane and also phase shifts, which are
253 applied for sampling incoming read data. The default value 0
254 means that no phase/delay adjustments are necessary. Properly
255 configuring this parameter increases reliability at high DRAM
258 config DRAM_DQS_GATING_DELAY
259 hex "sunxi dram dqs_gating_delay value"
262 Set the dram controller dqs_gating_delay parmeter. Each byte
263 encodes the DQS gating delay for each byte lane. The delay
264 granularity is 1/4 cycle. For example, the value 0x05060606
265 means that the delay is 5 quarter-cycles for one lane (1.25
266 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
267 The default value 0 means autodetection. The results of hardware
268 autodetection are not very reliable and depend on the chip
269 temperature (sometimes producing different results on cold start
270 and warm reboot). But the accuracy of hardware autodetection
271 is usually good enough, unless running at really high DRAM
272 clocks speeds (up to 600MHz). If unsure, keep as 0.
275 prompt "sunxi dram timings"
276 default DRAM_TIMINGS_VENDOR_MAGIC
278 Select the timings of the DDR3 chips.
280 config DRAM_TIMINGS_VENDOR_MAGIC
281 bool "Magic vendor timings from Android"
283 The same DRAM timings as in the Allwinner boot0 bootloader.
285 config DRAM_TIMINGS_DDR3_1066F_1333H
286 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
288 Use the timings of the standard JEDEC DDR3-1066F speed bin for
289 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
290 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
291 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
292 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
293 that down binning to DDR3-1066F is supported (because DDR3-1066F
294 uses a bit faster timings than DDR3-1333H).
296 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
297 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
299 Use the timings of the slowest possible JEDEC speed bin for the
300 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
301 DDR3-800E, DDR3-1066G or DDR3-1333J.
308 config DRAM_ODT_CORRECTION
309 int "sunxi dram odt correction value"
312 Set the dram odt correction value (range -255 - 255). In allwinner
313 fex files, this option is found in bits 8-15 of the u32 odt_en variable
314 in the [dram] section. When bit 31 of the odt_en variable is set
315 then the correction is negative. Usually the value for this is 0.
319 default 1008000000 if MACH_SUN4I
320 default 1008000000 if MACH_SUN5I
321 default 1008000000 if MACH_SUN6I
322 default 912000000 if MACH_SUN7I
323 default 1008000000 if MACH_SUN8I
324 default 1008000000 if MACH_SUN9I
325 default 816000000 if MACH_SUN50I
327 config SYS_CONFIG_NAME
328 default "sun4i" if MACH_SUN4I
329 default "sun5i" if MACH_SUN5I
330 default "sun6i" if MACH_SUN6I
331 default "sun7i" if MACH_SUN7I
332 default "sun8i" if MACH_SUN8I
333 default "sun9i" if MACH_SUN9I
334 default "sun50i" if MACH_SUN50I
343 bool "UART0 on MicroSD breakout board"
346 Repurpose the SD card slot for getting access to the UART0 serial
347 console. Primarily useful only for low level u-boot debugging on
348 tablets, where normal UART0 is difficult to access and requires
349 device disassembly and/or soldering. As the SD card can't be used
350 at the same time, the system can be only booted in the FEL mode.
351 Only enable this if you really know what you are doing.
353 config OLD_SUNXI_KERNEL_COMPAT
354 bool "Enable workarounds for booting old kernels"
357 Set this to enable various workarounds for old kernels, this results in
358 sub-optimal settings for newer kernels, only enable if needed.
361 string "MAC power pin"
364 Set the pin used to power the MAC. This takes a string in the format
365 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
368 string "Card detect pin for mmc0"
369 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
372 Set the card detect pin for mmc0, leave empty to not use cd. This
373 takes a string in the format understood by sunxi_name_to_gpio, e.g.
374 PH1 for pin 1 of port H.
377 string "Card detect pin for mmc1"
380 See MMC0_CD_PIN help text.
383 string "Card detect pin for mmc2"
386 See MMC0_CD_PIN help text.
389 string "Card detect pin for mmc3"
392 See MMC0_CD_PIN help text.
395 string "Pins for mmc1"
398 Set the pins used for mmc1, when applicable. This takes a string in the
399 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
402 string "Pins for mmc2"
405 See MMC1_PINS help text.
408 string "Pins for mmc3"
411 See MMC1_PINS help text.
413 config MMC_SUNXI_SLOT_EXTRA
414 int "mmc extra slot number"
417 sunxi builds always enable mmc0, some boards also have a second sdcard
418 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
421 config INITIAL_USB_SCAN_DELAY
422 int "delay initial usb scan by x ms to allow builtin devices to init"
425 Some boards have on board usb devices which need longer than the
426 USB spec's 1 second to connect from board powerup. Set this config
427 option to a non 0 value to add an extra delay before the first usb
431 string "Vbus enable pin for usb0 (otg)"
434 Set the Vbus enable pin for usb0 (otg). This takes a string in the
435 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
438 string "Vbus detect pin for usb0 (otg)"
441 Set the Vbus detect pin for usb0 (otg). This takes a string in the
442 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
445 string "ID detect pin for usb0 (otg)"
448 Set the ID detect pin for usb0 (otg). This takes a string in the
449 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
452 string "Vbus enable pin for usb1 (ehci0)"
453 default "PH6" if MACH_SUN4I || MACH_SUN7I
454 default "PH27" if MACH_SUN6I
456 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
457 a string in the format understood by sunxi_name_to_gpio, e.g.
458 PH1 for pin 1 of port H.
461 string "Vbus enable pin for usb2 (ehci1)"
462 default "PH3" if MACH_SUN4I || MACH_SUN7I
463 default "PH24" if MACH_SUN6I
465 See USB1_VBUS_PIN help text.
468 string "Vbus enable pin for usb3 (ehci2)"
471 See USB1_VBUS_PIN help text.
474 bool "Enable I2C/TWI controller 0"
475 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
476 default n if MACH_SUN6I || MACH_SUN8I
479 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
480 its clock and setting up the bus. This is especially useful on devices
481 with slaves connected to the bus or with pins exposed through e.g. an
482 expansion port/header.
485 bool "Enable I2C/TWI controller 1"
489 See I2C0_ENABLE help text.
492 bool "Enable I2C/TWI controller 2"
496 See I2C0_ENABLE help text.
498 if MACH_SUN6I || MACH_SUN7I
500 bool "Enable I2C/TWI controller 3"
504 See I2C0_ENABLE help text.
509 bool "Enable the PRCM I2C/TWI controller"
510 # This is used for the pmic on H3
511 default y if SY8106A_POWER
514 Set this to y to enable the I2C controller which is part of the PRCM.
519 bool "Enable I2C/TWI controller 4"
523 See I2C0_ENABLE help text.
527 bool "Enable support for gpio-s on axp PMICs"
530 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
533 bool "Enable graphical uboot console on HDMI, LCD or VGA"
534 depends on !MACH_SUN8I_A83T
535 depends on !MACH_SUNXI_H3_H5
536 depends on !MACH_SUN8I_R40
537 depends on !MACH_SUN8I_V3S
538 depends on !MACH_SUN9I
539 depends on !MACH_SUN50I
542 Say Y here to add support for using a cfb console on the HDMI, LCD
543 or VGA output found on most sunxi devices. See doc/README.video for
544 info on how to select the video output and mode.
547 bool "HDMI output support"
548 depends on VIDEO && !MACH_SUN8I
551 Say Y here to add support for outputting video over HDMI.
554 bool "VGA output support"
555 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
558 Say Y here to add support for outputting video over VGA.
560 config VIDEO_VGA_VIA_LCD
561 bool "VGA via LCD controller support"
562 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
565 Say Y here to add support for external DACs connected to the parallel
566 LCD interface driving a VGA connector, such as found on the
569 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
570 bool "Force sync active high for VGA via LCD controller support"
571 depends on VIDEO_VGA_VIA_LCD
574 Say Y here if you've a board which uses opendrain drivers for the vga
575 hsync and vsync signals. Opendrain drivers cannot generate steep enough
576 positive edges for a stable video output, so on boards with opendrain
577 drivers the sync signals must always be active high.
579 config VIDEO_VGA_EXTERNAL_DAC_EN
580 string "LCD panel power enable pin"
581 depends on VIDEO_VGA_VIA_LCD
584 Set the enable pin for the external VGA DAC. This takes a string in the
585 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
587 config VIDEO_COMPOSITE
588 bool "Composite video output support"
589 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
592 Say Y here to add support for outputting composite video.
594 config VIDEO_LCD_MODE
595 string "LCD panel timing details"
599 LCD panel timing details string, leave empty if there is no LCD panel.
600 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
601 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
602 Also see: http://linux-sunxi.org/LCD
604 config VIDEO_LCD_DCLK_PHASE
605 int "LCD panel display clock phase"
609 Select LCD panel display clock phase shift, range 0-3.
611 config VIDEO_LCD_POWER
612 string "LCD panel power enable pin"
616 Set the power enable pin for the LCD panel. This takes a string in the
617 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
619 config VIDEO_LCD_RESET
620 string "LCD panel reset pin"
624 Set the reset pin for the LCD panel. This takes a string in the format
625 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
627 config VIDEO_LCD_BL_EN
628 string "LCD panel backlight enable pin"
632 Set the backlight enable pin for the LCD panel. This takes a string in the
633 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
636 config VIDEO_LCD_BL_PWM
637 string "LCD panel backlight pwm pin"
641 Set the backlight pwm pin for the LCD panel. This takes a string in the
642 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
644 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
645 bool "LCD panel backlight pwm is inverted"
649 Set this if the backlight pwm output is active low.
651 config VIDEO_LCD_PANEL_I2C
652 bool "LCD panel needs to be configured via i2c"
657 Say y here if the LCD panel needs to be configured via i2c. This
658 will add a bitbang i2c controller using gpios to talk to the LCD.
660 config VIDEO_LCD_PANEL_I2C_SDA
661 string "LCD panel i2c interface SDA pin"
662 depends on VIDEO_LCD_PANEL_I2C
665 Set the SDA pin for the LCD i2c interface. This takes a string in the
666 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
668 config VIDEO_LCD_PANEL_I2C_SCL
669 string "LCD panel i2c interface SCL pin"
670 depends on VIDEO_LCD_PANEL_I2C
673 Set the SCL pin for the LCD i2c interface. This takes a string in the
674 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
677 # Note only one of these may be selected at a time! But hidden choices are
678 # not supported by Kconfig
679 config VIDEO_LCD_IF_PARALLEL
682 config VIDEO_LCD_IF_LVDS
690 bool "Display Engine 2 video driver"
696 Say y here if you want to build DE2 video driver which is present on
697 newer SoCs. Currently only HDMI output is supported.
701 prompt "LCD panel support"
704 Select which type of LCD panel to support.
706 config VIDEO_LCD_PANEL_PARALLEL
707 bool "Generic parallel interface LCD panel"
708 select VIDEO_LCD_IF_PARALLEL
710 config VIDEO_LCD_PANEL_LVDS
711 bool "Generic lvds interface LCD panel"
712 select VIDEO_LCD_IF_LVDS
714 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
715 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
716 select VIDEO_LCD_SSD2828
717 select VIDEO_LCD_IF_PARALLEL
719 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
721 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
722 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
723 select VIDEO_LCD_ANX9804
724 select VIDEO_LCD_IF_PARALLEL
725 select VIDEO_LCD_PANEL_I2C
727 Select this for eDP LCD panels with 4 lanes running at 1.62G,
728 connected via an ANX9804 bridge chip.
730 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
731 bool "Hitachi tx18d42vm LCD panel"
732 select VIDEO_LCD_HITACHI_TX18D42VM
733 select VIDEO_LCD_IF_LVDS
735 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
737 config VIDEO_LCD_TL059WV5C0
738 bool "tl059wv5c0 LCD panel"
739 select VIDEO_LCD_PANEL_I2C
740 select VIDEO_LCD_IF_PARALLEL
742 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
743 Aigo M60/M608/M606 tablets.
748 string "SATA power pin"
751 Set the pins used to power the SATA. This takes a string in the
752 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
756 int "GMAC Transmit Clock Delay Chain"
759 Set the GMAC Transmit Clock Delay Chain value.
761 config SPL_STACK_R_ADDR
762 default 0x4fe00000 if MACH_SUN4I
763 default 0x4fe00000 if MACH_SUN5I
764 default 0x4fe00000 if MACH_SUN6I
765 default 0x4fe00000 if MACH_SUN7I
766 default 0x4fe00000 if MACH_SUN8I
767 default 0x2fe00000 if MACH_SUN9I
768 default 0x4fe00000 if MACH_SUN50I