1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
6 * Copyright (C) 2014 Roman Byshko <rbyshko@gmail.com>
9 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/cpu.h>
15 #include <asm/arch/usb_phy.h>
20 #if defined(CONFIG_MACH_SUN4I) || \
21 defined(CONFIG_MACH_SUN5I) || \
22 defined(CONFIG_MACH_SUN6I) || \
23 defined(CONFIG_MACH_SUN7I) || \
24 defined(CONFIG_MACH_SUN8I_A23) || \
25 defined(CONFIG_MACH_SUN9I)
26 #define SUNXI_USB_CSR 0x404
28 #define SUNXI_USB_CSR 0x410
31 #define SUNXI_USB_PMU_IRQ_ENABLE 0x800
32 #define SUNXI_USB_PASSBY_EN 1
34 #define SUNXI_EHCI_AHB_ICHR8_EN (1 << 10)
35 #define SUNXI_EHCI_AHB_INCR4_BURST_EN (1 << 9)
36 #define SUNXI_EHCI_AHB_INCRX_ALIGN_EN (1 << 8)
37 #define SUNXI_EHCI_ULPI_BYPASS_EN (1 << 0)
39 #define REG_PHY_UNK_H3 0x420
40 #define REG_PMU_UNK_H3 0x810
42 /* A83T specific control bits for PHY0 */
43 #define SUNXI_PHY_CTL_VBUSVLDEXT BIT(5)
44 #define SUNXI_PHY_CTL_SIDDQ BIT(3)
46 /* A83T HSIC specific bits */
47 #define SUNXI_EHCI_HS_FORCE BIT(20)
48 #define SUNXI_EHCI_CONNECT_DET BIT(17)
49 #define SUNXI_EHCI_CONNECT_INT BIT(16)
50 #define SUNXI_EHCI_HSIC BIT(1)
52 static struct sunxi_usb_phy {
63 .usb_rst_mask = CCM_USB_CTRL_PHY0_RST | CCM_USB_CTRL_PHY0_CLK,
65 .base = SUNXI_USB0_BASE,
68 .usb_rst_mask = CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK,
70 .base = SUNXI_USB1_BASE,
72 #if CONFIG_SUNXI_USB_PHYS >= 3
74 #ifdef CONFIG_MACH_SUN8I_A83T
75 .usb_rst_mask = CCM_USB_CTRL_HSIC_RST | CCM_USB_CTRL_HSIC_CLK |
78 .usb_rst_mask = CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK,
81 .base = SUNXI_USB2_BASE,
84 #if CONFIG_SUNXI_USB_PHYS >= 4
86 .usb_rst_mask = CCM_USB_CTRL_PHY3_RST | CCM_USB_CTRL_PHY3_CLK,
88 .base = SUNXI_USB3_BASE,
93 static int initial_usb_scan_delay = CONFIG_INITIAL_USB_SCAN_DELAY;
95 static int get_vbus_gpio(int index)
98 case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_PIN);
99 case 1: return sunxi_name_to_gpio(CONFIG_USB1_VBUS_PIN);
100 case 2: return sunxi_name_to_gpio(CONFIG_USB2_VBUS_PIN);
101 case 3: return sunxi_name_to_gpio(CONFIG_USB3_VBUS_PIN);
106 static int get_vbus_detect_gpio(int index)
109 case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_DET);
114 static int get_id_detect_gpio(int index)
117 case 0: return sunxi_name_to_gpio(CONFIG_USB0_ID_DET);
122 __maybe_unused static void usb_phy_write(struct sunxi_usb_phy *phy, int addr,
125 int j = 0, usbc_bit = 0;
126 void *dest = (void *)SUNXI_USB0_BASE + SUNXI_USB_CSR;
128 #ifdef CONFIG_MACH_SUN8I_A33
129 /* CSR needs to be explicitly initialized to 0 on A33 */
133 usbc_bit = 1 << (phy->id * 2);
134 for (j = 0; j < len; j++) {
135 /* set the bit address to be written */
136 clrbits_le32(dest, 0xff << 8);
137 setbits_le32(dest, (addr + j) << 8);
139 clrbits_le32(dest, usbc_bit);
142 setbits_le32(dest, 1 << 7);
144 clrbits_le32(dest, 1 << 7);
146 setbits_le32(dest, usbc_bit);
148 clrbits_le32(dest, usbc_bit);
154 #if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
155 static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)
157 #if defined CONFIG_MACH_SUNXI_H3_H5
159 clrbits_le32(SUNXI_USBPHY_BASE + REG_PHY_UNK_H3, 0x01);
161 clrbits_le32(phy->base + REG_PMU_UNK_H3, 0x02);
163 #elif defined CONFIG_MACH_SUN8I_A83T
164 static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)
168 static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)
170 /* The following comments are machine
171 * translated from Chinese, you have been warned!
174 /* Regulation 45 ohms */
176 usb_phy_write(phy, 0x0c, 0x01, 1);
178 /* adjust PHY's magnitude and rate */
179 usb_phy_write(phy, 0x20, 0x14, 5);
181 /* threshold adjustment disconnect */
182 #if defined CONFIG_MACH_SUN5I || defined CONFIG_MACH_SUN7I
183 usb_phy_write(phy, 0x2a, 2, 2);
185 usb_phy_write(phy, 0x2a, 3, 2);
192 static void sunxi_usb_phy_passby(struct sunxi_usb_phy *phy, int enable)
194 unsigned long bits = 0;
197 addr = (void *)phy->base + SUNXI_USB_PMU_IRQ_ENABLE;
199 bits = SUNXI_EHCI_AHB_ICHR8_EN |
200 SUNXI_EHCI_AHB_INCR4_BURST_EN |
201 SUNXI_EHCI_AHB_INCRX_ALIGN_EN |
202 SUNXI_EHCI_ULPI_BYPASS_EN;
204 #ifdef CONFIG_MACH_SUN8I_A83T
206 bits |= SUNXI_EHCI_HS_FORCE |
207 SUNXI_EHCI_CONNECT_INT |
212 setbits_le32(addr, bits);
214 clrbits_le32(addr, bits);
219 void sunxi_usb_phy_enable_squelch_detect(int index, int enable)
221 #ifndef CONFIG_MACH_SUN8I_A83T
222 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
224 usb_phy_write(phy, 0x3c, enable ? 0 : 2, 2);
228 void sunxi_usb_phy_init(int index)
230 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
231 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
234 if (phy->init_count != 1)
237 setbits_le32(&ccm->usb_clk_cfg, phy->usb_rst_mask);
239 sunxi_usb_phy_config(phy);
242 sunxi_usb_phy_passby(phy, SUNXI_USB_PASSBY_EN);
244 #ifdef CONFIG_MACH_SUN8I_A83T
246 setbits_le32(SUNXI_USB0_BASE + SUNXI_USB_CSR,
247 SUNXI_PHY_CTL_VBUSVLDEXT);
248 clrbits_le32(SUNXI_USB0_BASE + SUNXI_USB_CSR,
249 SUNXI_PHY_CTL_SIDDQ);
254 void sunxi_usb_phy_exit(int index)
256 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
257 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
260 if (phy->init_count != 0)
264 sunxi_usb_phy_passby(phy, !SUNXI_USB_PASSBY_EN);
266 #ifdef CONFIG_MACH_SUN8I_A83T
268 setbits_le32(SUNXI_USB0_BASE + SUNXI_USB_CSR,
269 SUNXI_PHY_CTL_SIDDQ);
273 clrbits_le32(&ccm->usb_clk_cfg, phy->usb_rst_mask);
276 void sunxi_usb_phy_power_on(int index)
278 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
280 if (initial_usb_scan_delay) {
281 mdelay(initial_usb_scan_delay);
282 initial_usb_scan_delay = 0;
285 phy->power_on_count++;
286 if (phy->power_on_count != 1)
289 if (phy->gpio_vbus >= 0)
290 gpio_set_value(phy->gpio_vbus, 1);
293 void sunxi_usb_phy_power_off(int index)
295 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
297 phy->power_on_count--;
298 if (phy->power_on_count != 0)
301 if (phy->gpio_vbus >= 0)
302 gpio_set_value(phy->gpio_vbus, 0);
305 int sunxi_usb_phy_vbus_detect(int index)
307 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
308 int err, retries = 3;
310 if (phy->gpio_vbus_det < 0)
311 return phy->gpio_vbus_det;
313 err = gpio_get_value(phy->gpio_vbus_det);
315 * Vbus may have been provided by the board and just been turned of
316 * some milliseconds ago on reset, what we're measuring then is a
317 * residual charge on Vbus, sleep a bit and try again.
319 while (err > 0 && retries--) {
321 err = gpio_get_value(phy->gpio_vbus_det);
327 int sunxi_usb_phy_id_detect(int index)
329 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
331 if (phy->gpio_id_det < 0)
332 return phy->gpio_id_det;
334 return gpio_get_value(phy->gpio_id_det);
337 int sunxi_usb_phy_probe(void)
339 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
340 struct sunxi_usb_phy *phy;
343 for (i = 0; i < CONFIG_SUNXI_USB_PHYS; i++) {
344 phy = &sunxi_usb_phy[i];
346 phy->gpio_vbus = get_vbus_gpio(i);
347 if (phy->gpio_vbus >= 0) {
348 ret = gpio_request(phy->gpio_vbus, "usb_vbus");
351 ret = gpio_direction_output(phy->gpio_vbus, 0);
356 phy->gpio_vbus_det = get_vbus_detect_gpio(i);
357 if (phy->gpio_vbus_det >= 0) {
358 ret = gpio_request(phy->gpio_vbus_det, "usb_vbus_det");
361 ret = gpio_direction_input(phy->gpio_vbus_det);
366 phy->gpio_id_det = get_id_detect_gpio(i);
367 if (phy->gpio_id_det >= 0) {
368 ret = gpio_request(phy->gpio_id_det, "usb_id_det");
371 ret = gpio_direction_input(phy->gpio_id_det);
374 sunxi_gpio_set_pull(phy->gpio_id_det,
379 setbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
384 int sunxi_usb_phy_remove(void)
386 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
387 struct sunxi_usb_phy *phy;
390 clrbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
392 for (i = 0; i < CONFIG_SUNXI_USB_PHYS; i++) {
393 phy = &sunxi_usb_phy[i];
395 if (phy->gpio_vbus >= 0)
396 gpio_free(phy->gpio_vbus);
398 if (phy->gpio_vbus_det >= 0)
399 gpio_free(phy->gpio_vbus_det);
401 if (phy->gpio_id_det >= 0)
402 gpio_free(phy->gpio_id_det);