4 * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
5 * Copyright (C) 2014 Roman Byshko <rbyshko@gmail.com>
8 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
10 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/clock.h>
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/usb_phy.h>
21 #define SUNXI_USB_PMU_IRQ_ENABLE 0x800
22 #ifdef CONFIG_MACH_SUN8I_A33
23 #define SUNXI_USB_CSR 0x410
25 #define SUNXI_USB_CSR 0x404
27 #define SUNXI_USB_PASSBY_EN 1
29 #define SUNXI_EHCI_AHB_ICHR8_EN (1 << 10)
30 #define SUNXI_EHCI_AHB_INCR4_BURST_EN (1 << 9)
31 #define SUNXI_EHCI_AHB_INCRX_ALIGN_EN (1 << 8)
32 #define SUNXI_EHCI_ULPI_BYPASS_EN (1 << 0)
34 #define REG_PHY_UNK_H3 0x420
35 #define REG_PMU_UNK_H3 0x810
37 /* A83T specific control bits for PHY0 */
38 #define SUNXI_PHY_CTL_VBUSVLDEXT BIT(5)
39 #define SUNXI_PHY_CTL_SIDDQ BIT(3)
41 /* A83T HSIC specific bits */
42 #define SUNXI_EHCI_HS_FORCE BIT(20)
43 #define SUNXI_EHCI_CONNECT_DET BIT(17)
44 #define SUNXI_EHCI_CONNECT_INT BIT(16)
45 #define SUNXI_EHCI_HSIC BIT(1)
47 static struct sunxi_usb_phy {
58 .usb_rst_mask = CCM_USB_CTRL_PHY0_RST | CCM_USB_CTRL_PHY0_CLK,
60 .base = SUNXI_USB0_BASE,
63 .usb_rst_mask = CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK,
65 .base = SUNXI_USB1_BASE,
67 #if CONFIG_SUNXI_USB_PHYS >= 3
69 #ifdef CONFIG_MACH_SUN8I_A83T
70 .usb_rst_mask = CCM_USB_CTRL_HSIC_RST | CCM_USB_CTRL_HSIC_CLK |
73 .usb_rst_mask = CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK,
76 .base = SUNXI_USB2_BASE,
79 #if CONFIG_SUNXI_USB_PHYS >= 4
81 .usb_rst_mask = CCM_USB_CTRL_PHY3_RST | CCM_USB_CTRL_PHY3_CLK,
83 .base = SUNXI_USB3_BASE,
88 static int get_vbus_gpio(int index)
91 case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_PIN);
92 case 1: return sunxi_name_to_gpio(CONFIG_USB1_VBUS_PIN);
93 case 2: return sunxi_name_to_gpio(CONFIG_USB2_VBUS_PIN);
94 case 3: return sunxi_name_to_gpio(CONFIG_USB3_VBUS_PIN);
99 static int get_vbus_detect_gpio(int index)
102 case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_DET);
107 static int get_id_detect_gpio(int index)
110 case 0: return sunxi_name_to_gpio(CONFIG_USB0_ID_DET);
115 __maybe_unused static void usb_phy_write(struct sunxi_usb_phy *phy, int addr,
118 int j = 0, usbc_bit = 0;
119 void *dest = (void *)SUNXI_USB0_BASE + SUNXI_USB_CSR;
121 #ifdef CONFIG_MACH_SUN8I_A33
122 /* CSR needs to be explicitly initialized to 0 on A33 */
126 usbc_bit = 1 << (phy->id * 2);
127 for (j = 0; j < len; j++) {
128 /* set the bit address to be written */
129 clrbits_le32(dest, 0xff << 8);
130 setbits_le32(dest, (addr + j) << 8);
132 clrbits_le32(dest, usbc_bit);
135 setbits_le32(dest, 1 << 7);
137 clrbits_le32(dest, 1 << 7);
139 setbits_le32(dest, usbc_bit);
141 clrbits_le32(dest, usbc_bit);
147 #if defined CONFIG_MACH_SUN8I_H3
148 static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)
151 clrbits_le32(SUNXI_USBPHY_BASE + REG_PHY_UNK_H3, 0x01);
153 clrbits_le32(phy->base + REG_PMU_UNK_H3, 0x02);
155 #elif defined CONFIG_MACH_SUN8I_A83T
156 static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)
160 static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)
162 /* The following comments are machine
163 * translated from Chinese, you have been warned!
166 /* Regulation 45 ohms */
168 usb_phy_write(phy, 0x0c, 0x01, 1);
170 /* adjust PHY's magnitude and rate */
171 usb_phy_write(phy, 0x20, 0x14, 5);
173 /* threshold adjustment disconnect */
174 #if defined CONFIG_MACH_SUN5I || defined CONFIG_MACH_SUN7I
175 usb_phy_write(phy, 0x2a, 2, 2);
177 usb_phy_write(phy, 0x2a, 3, 2);
184 static void sunxi_usb_phy_passby(struct sunxi_usb_phy *phy, int enable)
186 unsigned long bits = 0;
189 addr = (void *)phy->base + SUNXI_USB_PMU_IRQ_ENABLE;
191 bits = SUNXI_EHCI_AHB_ICHR8_EN |
192 SUNXI_EHCI_AHB_INCR4_BURST_EN |
193 SUNXI_EHCI_AHB_INCRX_ALIGN_EN |
194 SUNXI_EHCI_ULPI_BYPASS_EN;
196 #ifdef CONFIG_MACH_SUN8I_A83T
198 bits |= SUNXI_EHCI_HS_FORCE |
199 SUNXI_EHCI_CONNECT_INT |
204 setbits_le32(addr, bits);
206 clrbits_le32(addr, bits);
211 void sunxi_usb_phy_enable_squelch_detect(int index, int enable)
213 #ifndef CONFIG_MACH_SUN8I_A83T
214 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
216 usb_phy_write(phy, 0x3c, enable ? 0 : 2, 2);
220 void sunxi_usb_phy_init(int index)
222 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
223 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
226 if (phy->init_count != 1)
229 setbits_le32(&ccm->usb_clk_cfg, phy->usb_rst_mask);
231 sunxi_usb_phy_config(phy);
234 sunxi_usb_phy_passby(phy, SUNXI_USB_PASSBY_EN);
236 #ifdef CONFIG_MACH_SUN8I_A83T
238 setbits_le32(SUNXI_USB0_BASE + SUNXI_USB_CSR,
239 SUNXI_PHY_CTL_VBUSVLDEXT);
240 clrbits_le32(SUNXI_USB0_BASE + SUNXI_USB_CSR,
241 SUNXI_PHY_CTL_SIDDQ);
246 void sunxi_usb_phy_exit(int index)
248 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
249 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
252 if (phy->init_count != 0)
256 sunxi_usb_phy_passby(phy, !SUNXI_USB_PASSBY_EN);
258 #ifdef CONFIG_MACH_SUN8I_A83T
260 setbits_le32(SUNXI_USB0_BASE + SUNXI_USB_CSR,
261 SUNXI_PHY_CTL_SIDDQ);
265 clrbits_le32(&ccm->usb_clk_cfg, phy->usb_rst_mask);
268 void sunxi_usb_phy_power_on(int index)
270 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
272 phy->power_on_count++;
273 if (phy->power_on_count != 1)
276 if (phy->gpio_vbus >= 0)
277 gpio_set_value(phy->gpio_vbus, 1);
280 void sunxi_usb_phy_power_off(int index)
282 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
284 phy->power_on_count--;
285 if (phy->power_on_count != 0)
288 if (phy->gpio_vbus >= 0)
289 gpio_set_value(phy->gpio_vbus, 0);
292 int sunxi_usb_phy_power_is_on(int index)
294 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
296 return phy->power_on_count > 0;
299 int sunxi_usb_phy_vbus_detect(int index)
301 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
302 int err, retries = 3;
304 if (phy->gpio_vbus_det < 0)
305 return phy->gpio_vbus_det;
307 err = gpio_get_value(phy->gpio_vbus_det);
309 * Vbus may have been provided by the board and just been turned of
310 * some milliseconds ago on reset, what we're measuring then is a
311 * residual charge on Vbus, sleep a bit and try again.
313 while (err > 0 && retries--) {
315 err = gpio_get_value(phy->gpio_vbus_det);
321 int sunxi_usb_phy_id_detect(int index)
323 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
325 if (phy->gpio_id_det < 0)
326 return phy->gpio_id_det;
328 return gpio_get_value(phy->gpio_id_det);
331 int sunxi_usb_phy_probe(void)
333 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
334 struct sunxi_usb_phy *phy;
337 for (i = 0; i < CONFIG_SUNXI_USB_PHYS; i++) {
338 phy = &sunxi_usb_phy[i];
340 phy->gpio_vbus = get_vbus_gpio(i);
341 if (phy->gpio_vbus >= 0) {
342 ret = gpio_request(phy->gpio_vbus, "usb_vbus");
345 ret = gpio_direction_output(phy->gpio_vbus, 0);
350 phy->gpio_vbus_det = get_vbus_detect_gpio(i);
351 if (phy->gpio_vbus_det >= 0) {
352 ret = gpio_request(phy->gpio_vbus_det, "usb_vbus_det");
355 ret = gpio_direction_input(phy->gpio_vbus_det);
360 phy->gpio_id_det = get_id_detect_gpio(i);
361 if (phy->gpio_id_det >= 0) {
362 ret = gpio_request(phy->gpio_id_det, "usb_id_det");
365 ret = gpio_direction_input(phy->gpio_id_det);
368 sunxi_gpio_set_pull(phy->gpio_id_det,
373 setbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
378 int sunxi_usb_phy_remove(void)
380 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
381 struct sunxi_usb_phy *phy;
384 clrbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
386 for (i = 0; i < CONFIG_SUNXI_USB_PHYS; i++) {
387 phy = &sunxi_usb_phy[i];
389 if (phy->gpio_vbus >= 0)
390 gpio_free(phy->gpio_vbus);
392 if (phy->gpio_vbus_det >= 0)
393 gpio_free(phy->gpio_vbus_det);
395 if (phy->gpio_id_det >= 0)
396 gpio_free(phy->gpio_id_det);