2 * (C) Copyright 2010,2011
3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
12 #include <linux/compiler.h>
13 #include <linux/sizes.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/funcmux.h>
17 #include <asm/arch/pinmux.h>
18 #include <asm/arch/pmu.h>
19 #include <asm/arch/tegra.h>
20 #include <asm/arch-tegra/ap.h>
21 #include <asm/arch-tegra/board.h>
22 #include <asm/arch-tegra/clk_rst.h>
23 #include <asm/arch-tegra/pmc.h>
24 #include <asm/arch-tegra/sys_proto.h>
25 #include <asm/arch-tegra/uart.h>
26 #include <asm/arch-tegra/warmboot.h>
27 #include <asm/arch-tegra/gpu.h>
28 #ifdef CONFIG_TEGRA_CLOCK_SCALING
29 #include <asm/arch/emc.h>
31 #include <asm/arch-tegra/usb.h>
32 #ifdef CONFIG_USB_EHCI_TEGRA
35 #ifdef CONFIG_TEGRA_MMC
36 #include <asm/arch-tegra/mmc.h>
38 #include <asm/arch-tegra/xusb-padctl.h>
39 #include <power/as3722.h>
44 DECLARE_GLOBAL_DATA_PTR;
46 #ifdef CONFIG_SPL_BUILD
47 /* TODO(sjg@chromium.org): Remove once SPL supports device tree */
48 U_BOOT_DEVICE(tegra_gpios) = {
53 __weak void pinmux_init(void) {}
54 __weak void pin_mux_usb(void) {}
55 __weak void pin_mux_spi(void) {}
56 __weak void pin_mux_mmc(void) {}
57 __weak void gpio_early_init_uart(void) {}
58 __weak void pin_mux_display(void) {}
59 __weak void start_cpu_fan(void) {}
61 #if defined(CONFIG_TEGRA_NAND)
62 __weak void pin_mux_nand(void)
64 funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT);
69 * Routine: power_det_init
70 * Description: turn off power detects
72 static void power_det_init(void)
74 #if defined(CONFIG_TEGRA20)
75 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
77 /* turn off power detects */
78 writel(0, &pmc->pmc_pwr_det_latch);
79 writel(0, &pmc->pmc_pwr_det);
83 __weak int tegra_board_id(void)
88 #ifdef CONFIG_DISPLAY_BOARDINFO
91 int board_id = tegra_board_id();
93 printf("Board: %s", CONFIG_TEGRA_BOARD_STRING);
95 printf(", ID: %d\n", board_id);
100 #endif /* CONFIG_DISPLAY_BOARDINFO */
102 __weak int tegra_lcd_pmic_init(int board_it)
107 __weak int nvidia_board_init(void)
113 * Routine: board_init
114 * Description: Early hardware init.
118 __maybe_unused int err;
119 __maybe_unused int board_id;
121 /* Do clocks and UART first so that printf() works */
127 #ifdef CONFIG_TEGRA_SPI
131 #ifdef CONFIG_TEGRA_MMC
135 /* Init is handled automatically in the driver-model case */
136 #if defined(CONFIG_DM_VIDEO)
139 /* boot param addr */
140 gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
144 #ifdef CONFIG_SYS_I2C_TEGRA
145 # ifdef CONFIG_TEGRA_PMU
146 if (pmu_set_nominal())
147 debug("Failed to select nominal voltages\n");
148 # ifdef CONFIG_TEGRA_CLOCK_SCALING
149 err = board_emc_init();
151 debug("Memory controller init failed: %d\n", err);
153 # endif /* CONFIG_TEGRA_PMU */
154 #ifdef CONFIG_AS3722_POWER
155 err = as3722_init(NULL);
156 if (err && err != -ENODEV)
159 #endif /* CONFIG_SYS_I2C_TEGRA */
161 #ifdef CONFIG_USB_EHCI_TEGRA
165 #if defined(CONFIG_DM_VIDEO)
166 board_id = tegra_board_id();
167 err = tegra_lcd_pmic_init(board_id);
172 #ifdef CONFIG_TEGRA_NAND
176 tegra_xusb_padctl_init(gd->fdt_blob);
178 #ifdef CONFIG_TEGRA_LP0
179 /* save Sdram params to PMC 2, 4, and 24 for WB0 */
180 warmboot_save_sdram_params();
182 /* prepare the WB code to LP0 location */
183 warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE);
185 return nvidia_board_init();
188 #ifdef CONFIG_BOARD_EARLY_INIT_F
189 static void __gpio_early_init(void)
193 void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init")));
195 int board_early_init_f(void)
197 #if defined(CONFIG_TEGRA_DISCONNECT_UDC_ON_BOOT)
198 #define USBCMD_FS2 (1 << 15)
200 struct usb_ctlr *usbctlr = (struct usb_ctlr *)0x7d000000;
201 writel(USBCMD_FS2, &usbctlr->usb_cmd);
205 /* Do any special system timer/TSC setup */
206 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
207 if (!tegra_cpu_is_non_secure())
214 /* Initialize periph GPIOs */
216 gpio_early_init_uart();
220 #endif /* EARLY_INIT */
222 int board_late_init(void)
224 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
225 if (tegra_cpu_is_non_secure()) {
226 printf("CPU is in NS mode\n");
227 setenv("cpu_ns_mode", "1");
229 setenv("cpu_ns_mode", "");
237 #if defined(CONFIG_TEGRA_MMC)
238 /* this is a weak define that we are overriding */
239 int board_mmc_init(bd_t *bd)
241 debug("%s called\n", __func__);
243 debug("%s: init MMC\n", __func__);
251 * In some SW environments, a memory carve-out exists to house a secure
252 * monitor, a trusted OS, and/or various statically allocated media buffers.
254 * This carveout exists at the highest possible address that is within a
255 * 32-bit physical address space.
257 * This function returns the total size of this carve-out. At present, the
258 * returned value is hard-coded for simplicity. In the future, it may be
259 * possible to determine the carve-out size:
260 * - By querying some run-time information source, such as:
261 * - A structure passed to U-Boot by earlier boot software.
263 * - A call into the secure monitor.
264 * - In the per-board U-Boot configuration header, based on knowledge of the
265 * SW environment that U-Boot is being built for.
267 * For now, we support two configurations in U-Boot:
268 * - 32-bit ports without any form of carve-out.
269 * - 64 bit ports which are assumed to use a carve-out of a conservatively
272 static ulong carveout_size(void)
282 * Determine the amount of usable RAM below 4GiB, taking into account any
283 * carve-out that may be assigned.
285 static ulong usable_ram_size_below_4g(void)
287 ulong total_size_below_4g;
288 ulong usable_size_below_4g;
291 * The total size of RAM below 4GiB is the lesser address of:
292 * (a) 2GiB itself (RAM starts at 2GiB, and 4GiB - 2GiB == 2GiB).
293 * (b) The size RAM physically present in the system.
295 if (gd->ram_size < SZ_2G)
296 total_size_below_4g = gd->ram_size;
298 total_size_below_4g = SZ_2G;
300 /* Calculate usable RAM by subtracting out any carve-out size */
301 usable_size_below_4g = total_size_below_4g - carveout_size();
303 return usable_size_below_4g;
307 * Represent all available RAM in either one or two banks.
309 * The first bank describes any usable RAM below 4GiB.
310 * The second bank describes any RAM above 4GiB.
312 * This split is driven by the following requirements:
313 * - The NVIDIA L4T kernel requires separate entries in the DT /memory/reg
314 * property for memory below and above the 4GiB boundary. The layout of that
315 * DT property is directly driven by the entries in the U-Boot bank array.
316 * - The potential existence of a carve-out at the end of RAM below 4GiB can
317 * only be represented using multiple banks.
319 * Explicitly removing the carve-out RAM from the bank entries makes the RAM
320 * layout a bit more obvious, e.g. when running "bdinfo" at the U-Boot
323 * This does mean that the DT U-Boot passes to the Linux kernel will not
324 * include this RAM in /memory/reg at all. An alternative would be to include
325 * all RAM in the U-Boot banks (and hence DT), and add a /memreserve/ node
326 * into DT to stop the kernel from using the RAM. IIUC, I don't /think/ the
327 * Linux kernel will ever need to access any RAM in* the carve-out via a CPU
328 * mapping, so either way is acceptable.
330 * On 32-bit systems, we never define a bank for RAM above 4GiB, since the
331 * start address of that bank cannot be represented in the 32-bit .size
334 void dram_init_banksize(void)
336 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
337 gd->bd->bi_dram[0].size = usable_ram_size_below_4g();
340 gd->pci_ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
343 #ifdef CONFIG_PHYS_64BIT
344 if (gd->ram_size > SZ_2G) {
345 gd->bd->bi_dram[1].start = 0x100000000;
346 gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G;
350 gd->bd->bi_dram[1].start = 0;
351 gd->bd->bi_dram[1].size = 0;
356 * Most hardware on 64-bit Tegra is still restricted to DMA to the lower
357 * 32-bits of the physical address space. Cap the maximum usable RAM area
358 * at 4 GiB to avoid DMA buffers from being allocated beyond the 32-bit
359 * boundary that most devices can address. Also, don't let U-Boot use any
360 * carve-out, as mentioned above.
362 * This function is called before dram_init_banksize(), so we can't simply
363 * return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size.
365 ulong board_get_usable_ram_top(ulong total_size)
367 return CONFIG_SYS_SDRAM_BASE + usable_ram_size_below_4g();