2 * (C) Copyright 2010,2011
3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
12 #include <linux/compiler.h>
13 #include <linux/sizes.h>
15 #include <asm/arch/clock.h>
17 #include <asm/arch/display.h>
19 #include <asm/arch/funcmux.h>
20 #include <asm/arch/pinmux.h>
21 #include <asm/arch/pmu.h>
22 #ifdef CONFIG_PWM_TEGRA
23 #include <asm/arch/pwm.h>
25 #include <asm/arch/tegra.h>
26 #include <asm/arch-tegra/ap.h>
27 #include <asm/arch-tegra/board.h>
28 #include <asm/arch-tegra/clk_rst.h>
29 #include <asm/arch-tegra/pmc.h>
30 #include <asm/arch-tegra/sys_proto.h>
31 #include <asm/arch-tegra/uart.h>
32 #include <asm/arch-tegra/warmboot.h>
33 #include <asm/arch-tegra/gpu.h>
34 #ifdef CONFIG_TEGRA_CLOCK_SCALING
35 #include <asm/arch/emc.h>
37 #include <asm/arch-tegra/usb.h>
38 #ifdef CONFIG_USB_EHCI_TEGRA
41 #ifdef CONFIG_TEGRA_MMC
42 #include <asm/arch-tegra/tegra_mmc.h>
43 #include <asm/arch-tegra/mmc.h>
45 #include <asm/arch-tegra/xusb-padctl.h>
46 #include <power/as3722.h>
51 DECLARE_GLOBAL_DATA_PTR;
53 #ifdef CONFIG_SPL_BUILD
54 /* TODO(sjg@chromium.org): Remove once SPL supports device tree */
55 U_BOOT_DEVICE(tegra_gpios) = {
60 __weak void pinmux_init(void) {}
61 __weak void pin_mux_usb(void) {}
62 __weak void pin_mux_spi(void) {}
63 __weak void gpio_early_init_uart(void) {}
64 __weak void pin_mux_display(void) {}
65 __weak void start_cpu_fan(void) {}
67 #if defined(CONFIG_TEGRA_NAND)
68 __weak void pin_mux_nand(void)
70 funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT);
75 * Routine: power_det_init
76 * Description: turn off power detects
78 static void power_det_init(void)
80 #if defined(CONFIG_TEGRA20)
81 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
83 /* turn off power detects */
84 writel(0, &pmc->pmc_pwr_det_latch);
85 writel(0, &pmc->pmc_pwr_det);
89 __weak int tegra_board_id(void)
94 #ifdef CONFIG_DISPLAY_BOARDINFO
97 int board_id = tegra_board_id();
99 printf("Board: %s", CONFIG_TEGRA_BOARD_STRING);
101 printf(", ID: %d\n", board_id);
106 #endif /* CONFIG_DISPLAY_BOARDINFO */
108 __weak int tegra_lcd_pmic_init(int board_it)
113 __weak int nvidia_board_init(void)
119 * Routine: board_init
120 * Description: Early hardware init.
124 __maybe_unused int err;
125 __maybe_unused int board_id;
127 /* Do clocks and UART first so that printf() works */
133 #ifdef CONFIG_TEGRA_SPI
137 /* Init is handled automatically in the driver-model case */
138 #if defined(CONFIG_PWM_TEGRA) && !defined(CONFIG_PWM)
139 if (pwm_init(gd->fdt_blob))
140 debug("%s: Failed to init pwm\n", __func__);
142 #if defined(CONFIG_LCD) || defined(CONFIG_DM_VIDEO)
146 tegra_lcd_check_next_stage(gd->fdt_blob, 0);
148 /* boot param addr */
149 gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
153 #ifdef CONFIG_SYS_I2C_TEGRA
154 # ifdef CONFIG_TEGRA_PMU
155 if (pmu_set_nominal())
156 debug("Failed to select nominal voltages\n");
157 # ifdef CONFIG_TEGRA_CLOCK_SCALING
158 err = board_emc_init();
160 debug("Memory controller init failed: %d\n", err);
162 # endif /* CONFIG_TEGRA_PMU */
163 #ifdef CONFIG_AS3722_POWER
164 err = as3722_init(NULL);
165 if (err && err != -ENODEV)
168 #endif /* CONFIG_SYS_I2C_TEGRA */
170 #ifdef CONFIG_USB_EHCI_TEGRA
174 #if defined(CONFIG_LCD) || defined(CONFIG_DM_VIDEO)
175 board_id = tegra_board_id();
176 err = tegra_lcd_pmic_init(board_id);
181 tegra_lcd_check_next_stage(gd->fdt_blob, 0);
184 #ifdef CONFIG_TEGRA_NAND
188 tegra_xusb_padctl_init(gd->fdt_blob);
190 #ifdef CONFIG_TEGRA_LP0
191 /* save Sdram params to PMC 2, 4, and 24 for WB0 */
192 warmboot_save_sdram_params();
194 /* prepare the WB code to LP0 location */
195 warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE);
197 return nvidia_board_init();
200 #ifdef CONFIG_BOARD_EARLY_INIT_F
201 static void __gpio_early_init(void)
205 void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init")));
207 int board_early_init_f(void)
209 #if defined(CONFIG_TEGRA_DISCONNECT_UDC_ON_BOOT)
210 #define USBCMD_FS2 (1 << 15)
212 struct usb_ctlr *usbctlr = (struct usb_ctlr *)0x7d000000;
213 writel(USBCMD_FS2, &usbctlr->usb_cmd);
217 /* Do any special system timer/TSC setup */
218 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
219 if (!tegra_cpu_is_non_secure())
226 /* Initialize periph GPIOs */
228 gpio_early_init_uart();
230 tegra_lcd_early_init(gd->fdt_blob);
235 #endif /* EARLY_INIT */
237 int board_late_init(void)
240 /* Make sure we finish initing the LCD */
241 tegra_lcd_check_next_stage(gd->fdt_blob, 1);
243 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
244 if (tegra_cpu_is_non_secure()) {
245 printf("CPU is in NS mode\n");
246 setenv("cpu_ns_mode", "1");
248 setenv("cpu_ns_mode", "");
256 #if defined(CONFIG_TEGRA_MMC)
257 __weak void pin_mux_mmc(void)
261 /* this is a weak define that we are overriding */
262 int board_mmc_init(bd_t *bd)
264 debug("%s called\n", __func__);
266 /* Enable muxes, etc. for SDMMC controllers */
269 debug("%s: init MMC\n", __func__);
275 void pad_init_mmc(struct mmc_host *host)
277 #if defined(CONFIG_TEGRA30)
278 enum periph_id id = host->mmc_id;
281 debug("%s: sdmmc address = %08x, id = %d\n", __func__,
282 (unsigned int)host->reg, id);
284 /* Set the pad drive strength for SDMMC1 or 3 only */
285 if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) {
286 debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
291 val = readl(&host->reg->sdmemcmppadctl);
293 val |= MEMCOMP_PADCTRL_VREF;
294 writel(val, &host->reg->sdmemcmppadctl);
296 val = readl(&host->reg->autocalcfg);
298 val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED;
299 writel(val, &host->reg->autocalcfg);
305 * In some SW environments, a memory carve-out exists to house a secure
306 * monitor, a trusted OS, and/or various statically allocated media buffers.
308 * This carveout exists at the highest possible address that is within a
309 * 32-bit physical address space.
311 * This function returns the total size of this carve-out. At present, the
312 * returned value is hard-coded for simplicity. In the future, it may be
313 * possible to determine the carve-out size:
314 * - By querying some run-time information source, such as:
315 * - A structure passed to U-Boot by earlier boot software.
317 * - A call into the secure monitor.
318 * - In the per-board U-Boot configuration header, based on knowledge of the
319 * SW environment that U-Boot is being built for.
321 * For now, we support two configurations in U-Boot:
322 * - 32-bit ports without any form of carve-out.
323 * - 64 bit ports which are assumed to use a carve-out of a conservatively
326 static ulong carveout_size(void)
336 * Determine the amount of usable RAM below 4GiB, taking into account any
337 * carve-out that may be assigned.
339 static ulong usable_ram_size_below_4g(void)
341 ulong total_size_below_4g;
342 ulong usable_size_below_4g;
345 * The total size of RAM below 4GiB is the lesser address of:
346 * (a) 2GiB itself (RAM starts at 2GiB, and 4GiB - 2GiB == 2GiB).
347 * (b) The size RAM physically present in the system.
349 if (gd->ram_size < SZ_2G)
350 total_size_below_4g = gd->ram_size;
352 total_size_below_4g = SZ_2G;
354 /* Calculate usable RAM by subtracting out any carve-out size */
355 usable_size_below_4g = total_size_below_4g - carveout_size();
357 return usable_size_below_4g;
361 * Represent all available RAM in either one or two banks.
363 * The first bank describes any usable RAM below 4GiB.
364 * The second bank describes any RAM above 4GiB.
366 * This split is driven by the following requirements:
367 * - The NVIDIA L4T kernel requires separate entries in the DT /memory/reg
368 * property for memory below and above the 4GiB boundary. The layout of that
369 * DT property is directly driven by the entries in the U-Boot bank array.
370 * - The potential existence of a carve-out at the end of RAM below 4GiB can
371 * only be represented using multiple banks.
373 * Explicitly removing the carve-out RAM from the bank entries makes the RAM
374 * layout a bit more obvious, e.g. when running "bdinfo" at the U-Boot
377 * This does mean that the DT U-Boot passes to the Linux kernel will not
378 * include this RAM in /memory/reg at all. An alternative would be to include
379 * all RAM in the U-Boot banks (and hence DT), and add a /memreserve/ node
380 * into DT to stop the kernel from using the RAM. IIUC, I don't /think/ the
381 * Linux kernel will ever need to access any RAM in* the carve-out via a CPU
382 * mapping, so either way is acceptable.
384 * On 32-bit systems, we never define a bank for RAM above 4GiB, since the
385 * start address of that bank cannot be represented in the 32-bit .size
388 void dram_init_banksize(void)
390 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
391 gd->bd->bi_dram[0].size = usable_ram_size_below_4g();
394 gd->pci_ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
397 #ifdef CONFIG_PHYS_64BIT
398 if (gd->ram_size > SZ_2G) {
399 gd->bd->bi_dram[1].start = 0x100000000;
400 gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G;
404 gd->bd->bi_dram[1].start = 0;
405 gd->bd->bi_dram[1].size = 0;
410 * Most hardware on 64-bit Tegra is still restricted to DMA to the lower
411 * 32-bits of the physical address space. Cap the maximum usable RAM area
412 * at 4 GiB to avoid DMA buffers from being allocated beyond the 32-bit
413 * boundary that most devices can address. Also, don't let U-Boot use any
414 * carve-out, as mentioned above.
416 * This function is called before dram_init_banksize(), so we can't simply
417 * return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size.
419 ulong board_get_usable_ram_top(ulong total_size)
421 return CONFIG_SYS_SDRAM_BASE + usable_ram_size_below_4g();
425 * This function is called right before the kernel is booted. "blob" is the
426 * device tree that will be passed to the kernel.
428 int ft_system_setup(void *blob, bd_t *bd)
430 const char *gpu_path =
431 #if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
437 /* Enable GPU node if GPU setup has been performed */
438 if (gpu_path != NULL)
439 return tegra_gpu_enable_node(blob, gpu_path);