2 * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
3 * Copyright (c) 2011 The Chromium OS Authors.
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/pinmux.h>
12 /* return 1 if a pingrp is in range */
13 #define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PMUX_PINGRP_COUNT))
15 /* return 1 if a pmux_func is in range */
16 #define pmux_func_isvalid(func) \
17 (((func) >= 0) && ((func) < PMUX_FUNC_COUNT))
19 /* return 1 if a pin_pupd_is in range */
20 #define pmux_pin_pupd_isvalid(pupd) \
21 (((pupd) >= PMUX_PULL_NORMAL) && ((pupd) <= PMUX_PULL_UP))
23 /* return 1 if a pin_tristate_is in range */
24 #define pmux_pin_tristate_isvalid(tristate) \
25 (((tristate) >= PMUX_TRI_NORMAL) && ((tristate) <= PMUX_TRI_TRISTATE))
27 #ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
28 /* return 1 if a pin_io_is in range */
29 #define pmux_pin_io_isvalid(io) \
30 (((io) >= PMUX_PIN_OUTPUT) && ((io) <= PMUX_PIN_INPUT))
32 /* return 1 if a pin_lock is in range */
33 #define pmux_pin_lock_isvalid(lock) \
34 (((lock) >= PMUX_PIN_LOCK_DISABLE) && ((lock) <= PMUX_PIN_LOCK_ENABLE))
36 /* return 1 if a pin_od is in range */
37 #define pmux_pin_od_isvalid(od) \
38 (((od) >= PMUX_PIN_OD_DISABLE) && ((od) <= PMUX_PIN_OD_ENABLE))
40 /* return 1 if a pin_ioreset_is in range */
41 #define pmux_pin_ioreset_isvalid(ioreset) \
42 (((ioreset) >= PMUX_PIN_IO_RESET_DISABLE) && \
43 ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
45 #ifdef TEGRA_PMX_HAS_RCV_SEL
46 /* return 1 if a pin_rcv_sel_is in range */
47 #define pmux_pin_rcv_sel_isvalid(rcv_sel) \
48 (((rcv_sel) >= PMUX_PIN_RCV_SEL_NORMAL) && \
49 ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
50 #endif /* TEGRA_PMX_HAS_RCV_SEL */
51 #endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
53 #define _R(offset) (u32 *)(NV_PA_APB_MISC_BASE + (offset))
55 #if defined(CONFIG_TEGRA20)
57 #define MUX_REG(grp) _R(0x80 + ((tegra_soc_pingroups[grp].ctl_id / 16) * 4))
58 #define MUX_SHIFT(grp) ((tegra_soc_pingroups[grp].ctl_id % 16) * 2)
60 #define PULL_REG(grp) _R(0xa0 + ((tegra_soc_pingroups[grp].pull_id / 16) * 4))
61 #define PULL_SHIFT(grp) ((tegra_soc_pingroups[grp].pull_id % 16) * 2)
63 #define TRI_REG(grp) _R(0x14 + (((grp) / 32) * 4))
64 #define TRI_SHIFT(grp) ((grp) % 32)
68 #define REG(pin) _R(0x3000 + ((pin) * 4))
70 #define MUX_REG(pin) REG(pin)
71 #define MUX_SHIFT(pin) 0
73 #define PULL_REG(pin) REG(pin)
74 #define PULL_SHIFT(pin) 2
76 #define TRI_REG(pin) REG(pin)
77 #define TRI_SHIFT(pin) 4
79 #endif /* CONFIG_TEGRA20 */
81 #define DRV_REG(group) _R(0x868 + ((group) * 4))
86 #define IO_RESET_SHIFT 8
87 #define RCV_SEL_SHIFT 9
89 #if !defined(CONFIG_TEGRA20) && !defined(CONFIG_TEGRA30)
90 /* This register/field only exists on Tegra114 and later */
91 #define APB_MISC_PP_PINMUX_GLOBAL_0 0x40
92 #define CLAMP_INPUTS_WHEN_TRISTATED 1
94 void pinmux_set_tristate_input_clamping(void)
96 u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0);
98 setbits_le32(reg, CLAMP_INPUTS_WHEN_TRISTATED);
101 void pinmux_clear_tristate_input_clamping(void)
103 u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0);
105 clrbits_le32(reg, CLAMP_INPUTS_WHEN_TRISTATED);
109 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
111 u32 *reg = MUX_REG(pin);
115 if (func == PMUX_FUNC_DEFAULT)
118 /* Error check on pin and func */
119 assert(pmux_pingrp_isvalid(pin));
120 assert(pmux_func_isvalid(func));
122 if (func >= PMUX_FUNC_RSVD1) {
123 mux = (func - PMUX_FUNC_RSVD1) & 3;
125 /* Search for the appropriate function */
126 for (i = 0; i < 4; i++) {
127 if (tegra_soc_pingroups[pin].funcs[i] == func) {
136 val &= ~(3 << MUX_SHIFT(pin));
137 val |= (mux << MUX_SHIFT(pin));
141 void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
143 u32 *reg = PULL_REG(pin);
146 /* Error check on pin and pupd */
147 assert(pmux_pingrp_isvalid(pin));
148 assert(pmux_pin_pupd_isvalid(pupd));
151 val &= ~(3 << PULL_SHIFT(pin));
152 val |= (pupd << PULL_SHIFT(pin));
156 static void pinmux_set_tristate(enum pmux_pingrp pin, int tri)
158 u32 *reg = TRI_REG(pin);
161 /* Error check on pin */
162 assert(pmux_pingrp_isvalid(pin));
163 assert(pmux_pin_tristate_isvalid(tri));
166 if (tri == PMUX_TRI_TRISTATE)
167 val |= (1 << TRI_SHIFT(pin));
169 val &= ~(1 << TRI_SHIFT(pin));
173 void pinmux_tristate_enable(enum pmux_pingrp pin)
175 pinmux_set_tristate(pin, PMUX_TRI_TRISTATE);
178 void pinmux_tristate_disable(enum pmux_pingrp pin)
180 pinmux_set_tristate(pin, PMUX_TRI_NORMAL);
183 #ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
184 void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
189 if (io == PMUX_PIN_NONE)
192 /* Error check on pin and io */
193 assert(pmux_pingrp_isvalid(pin));
194 assert(pmux_pin_io_isvalid(io));
197 if (io == PMUX_PIN_INPUT)
198 val |= (io & 1) << IO_SHIFT;
200 val &= ~(1 << IO_SHIFT);
204 static void pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
209 if (lock == PMUX_PIN_LOCK_DEFAULT)
212 /* Error check on pin and lock */
213 assert(pmux_pingrp_isvalid(pin));
214 assert(pmux_pin_lock_isvalid(lock));
217 if (lock == PMUX_PIN_LOCK_ENABLE) {
218 val |= (1 << LOCK_SHIFT);
220 if (val & (1 << LOCK_SHIFT))
221 printf("%s: Cannot clear LOCK bit!\n", __func__);
222 val &= ~(1 << LOCK_SHIFT);
229 static void pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
234 if (od == PMUX_PIN_OD_DEFAULT)
237 /* Error check on pin and od */
238 assert(pmux_pingrp_isvalid(pin));
239 assert(pmux_pin_od_isvalid(od));
242 if (od == PMUX_PIN_OD_ENABLE)
243 val |= (1 << OD_SHIFT);
245 val &= ~(1 << OD_SHIFT);
251 static void pinmux_set_ioreset(enum pmux_pingrp pin,
252 enum pmux_pin_ioreset ioreset)
257 if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
260 /* Error check on pin and ioreset */
261 assert(pmux_pingrp_isvalid(pin));
262 assert(pmux_pin_ioreset_isvalid(ioreset));
265 if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
266 val |= (1 << IO_RESET_SHIFT);
268 val &= ~(1 << IO_RESET_SHIFT);
274 #ifdef TEGRA_PMX_HAS_RCV_SEL
275 static void pinmux_set_rcv_sel(enum pmux_pingrp pin,
276 enum pmux_pin_rcv_sel rcv_sel)
281 if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT)
284 /* Error check on pin and rcv_sel */
285 assert(pmux_pingrp_isvalid(pin));
286 assert(pmux_pin_rcv_sel_isvalid(rcv_sel));
289 if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH)
290 val |= (1 << RCV_SEL_SHIFT);
292 val &= ~(1 << RCV_SEL_SHIFT);
297 #endif /* TEGRA_PMX_HAS_RCV_SEL */
298 #endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
300 static void pinmux_config_pingrp(const struct pmux_pingrp_config *config)
302 enum pmux_pingrp pin = config->pingrp;
304 pinmux_set_func(pin, config->func);
305 pinmux_set_pullupdown(pin, config->pull);
306 pinmux_set_tristate(pin, config->tristate);
307 #ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
308 pinmux_set_io(pin, config->io);
309 pinmux_set_lock(pin, config->lock);
310 pinmux_set_od(pin, config->od);
311 pinmux_set_ioreset(pin, config->ioreset);
312 #ifdef TEGRA_PMX_HAS_RCV_SEL
313 pinmux_set_rcv_sel(pin, config->rcv_sel);
318 void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
323 for (i = 0; i < len; i++)
324 pinmux_config_pingrp(&config[i]);
327 #ifdef TEGRA_PMX_HAS_DRVGRPS
329 #define pmux_drvgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PMUX_DRVGRP_COUNT))
331 #define pmux_slw_isvalid(slw) \
332 (((slw) >= PMUX_SLWF_MIN) && ((slw) <= PMUX_SLWF_MAX))
334 #define pmux_drv_isvalid(drv) \
335 (((drv) >= PMUX_DRVUP_MIN) && ((drv) <= PMUX_DRVUP_MAX))
337 #define pmux_lpmd_isvalid(lpm) \
338 (((lpm) >= PMUX_LPMD_X8) && ((lpm) <= PMUX_LPMD_X))
340 #define pmux_schmt_isvalid(schmt) \
341 (((schmt) >= PMUX_SCHMT_DISABLE) && ((schmt) <= PMUX_SCHMT_ENABLE))
343 #define pmux_hsm_isvalid(hsm) \
344 (((hsm) >= PMUX_HSM_DISABLE) && ((hsm) <= PMUX_HSM_ENABLE))
347 #define SCHMT_SHIFT 3
349 #define LPMD_MASK (3 << LPMD_SHIFT)
351 * Note that the following DRV* and SLW* defines are accurate for many drive
352 * groups on many SoCs. We really need a per-group data structure to solve
353 * this, since the fields are in different positions/sizes in different
354 * registers (for different groups).
356 * On Tegra30/114/124, the DRV*_SHIFT values vary.
357 * On Tegra30, the SLW*_SHIFT values vary.
358 * On Tegra30/114/124/210, the DRV*_MASK values vary, although the values
359 * below are wide enough to cover the widest fields, and hopefully don't
360 * interfere with any other fields.
361 * On Tegra30, the SLW*_MASK values vary, but we can't use a value that's
362 * wide enough to cover all cases, since that would cause the field to
363 * overlap with other fields in the narrower cases.
365 #define DRVDN_SHIFT 12
366 #define DRVDN_MASK (0x7F << DRVDN_SHIFT)
367 #define DRVUP_SHIFT 20
368 #define DRVUP_MASK (0x7F << DRVUP_SHIFT)
369 #define SLWR_SHIFT 28
370 #define SLWR_MASK (3 << SLWR_SHIFT)
371 #define SLWF_SHIFT 30
372 #define SLWF_MASK (3 << SLWF_SHIFT)
374 static void pinmux_set_drvup_slwf(enum pmux_drvgrp grp, int slwf)
376 u32 *reg = DRV_REG(grp);
379 /* NONE means unspecified/do not change/use POR value */
380 if (slwf == PMUX_SLWF_NONE)
383 /* Error check on pad and slwf */
384 assert(pmux_drvgrp_isvalid(grp));
385 assert(pmux_slw_isvalid(slwf));
389 val |= (slwf << SLWF_SHIFT);
395 static void pinmux_set_drvdn_slwr(enum pmux_drvgrp grp, int slwr)
397 u32 *reg = DRV_REG(grp);
400 /* NONE means unspecified/do not change/use POR value */
401 if (slwr == PMUX_SLWR_NONE)
404 /* Error check on pad and slwr */
405 assert(pmux_drvgrp_isvalid(grp));
406 assert(pmux_slw_isvalid(slwr));
410 val |= (slwr << SLWR_SHIFT);
416 static void pinmux_set_drvup(enum pmux_drvgrp grp, int drvup)
418 u32 *reg = DRV_REG(grp);
421 /* NONE means unspecified/do not change/use POR value */
422 if (drvup == PMUX_DRVUP_NONE)
425 /* Error check on pad and drvup */
426 assert(pmux_drvgrp_isvalid(grp));
427 assert(pmux_drv_isvalid(drvup));
431 val |= (drvup << DRVUP_SHIFT);
437 static void pinmux_set_drvdn(enum pmux_drvgrp grp, int drvdn)
439 u32 *reg = DRV_REG(grp);
442 /* NONE means unspecified/do not change/use POR value */
443 if (drvdn == PMUX_DRVDN_NONE)
446 /* Error check on pad and drvdn */
447 assert(pmux_drvgrp_isvalid(grp));
448 assert(pmux_drv_isvalid(drvdn));
452 val |= (drvdn << DRVDN_SHIFT);
458 static void pinmux_set_lpmd(enum pmux_drvgrp grp, enum pmux_lpmd lpmd)
460 u32 *reg = DRV_REG(grp);
463 /* NONE means unspecified/do not change/use POR value */
464 if (lpmd == PMUX_LPMD_NONE)
467 /* Error check pad and lpmd value */
468 assert(pmux_drvgrp_isvalid(grp));
469 assert(pmux_lpmd_isvalid(lpmd));
473 val |= (lpmd << LPMD_SHIFT);
479 static void pinmux_set_schmt(enum pmux_drvgrp grp, enum pmux_schmt schmt)
481 u32 *reg = DRV_REG(grp);
484 /* NONE means unspecified/do not change/use POR value */
485 if (schmt == PMUX_SCHMT_NONE)
488 /* Error check pad */
489 assert(pmux_drvgrp_isvalid(grp));
490 assert(pmux_schmt_isvalid(schmt));
493 if (schmt == PMUX_SCHMT_ENABLE)
494 val |= (1 << SCHMT_SHIFT);
496 val &= ~(1 << SCHMT_SHIFT);
502 static void pinmux_set_hsm(enum pmux_drvgrp grp, enum pmux_hsm hsm)
504 u32 *reg = DRV_REG(grp);
507 /* NONE means unspecified/do not change/use POR value */
508 if (hsm == PMUX_HSM_NONE)
511 /* Error check pad */
512 assert(pmux_drvgrp_isvalid(grp));
513 assert(pmux_hsm_isvalid(hsm));
516 if (hsm == PMUX_HSM_ENABLE)
517 val |= (1 << HSM_SHIFT);
519 val &= ~(1 << HSM_SHIFT);
525 static void pinmux_config_drvgrp(const struct pmux_drvgrp_config *config)
527 enum pmux_drvgrp grp = config->drvgrp;
529 pinmux_set_drvup_slwf(grp, config->slwf);
530 pinmux_set_drvdn_slwr(grp, config->slwr);
531 pinmux_set_drvup(grp, config->drvup);
532 pinmux_set_drvdn(grp, config->drvdn);
533 pinmux_set_lpmd(grp, config->lpmd);
534 pinmux_set_schmt(grp, config->schmt);
535 pinmux_set_hsm(grp, config->hsm);
538 void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
543 for (i = 0; i < len; i++)
544 pinmux_config_drvgrp(&config[i]);
546 #endif /* TEGRA_PMX_HAS_DRVGRPS */