2 * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
3 * Copyright (c) 2011 The Chromium OS Authors.
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/pinmux.h>
12 /* return 1 if a pingrp is in range */
13 #define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PMUX_PINGRP_COUNT))
15 /* return 1 if a pmux_func is in range */
16 #define pmux_func_isvalid(func) \
17 (((func) >= 0) && ((func) < PMUX_FUNC_COUNT))
19 /* return 1 if a pin_pupd_is in range */
20 #define pmux_pin_pupd_isvalid(pupd) \
21 (((pupd) >= PMUX_PULL_NORMAL) && ((pupd) <= PMUX_PULL_UP))
23 /* return 1 if a pin_tristate_is in range */
24 #define pmux_pin_tristate_isvalid(tristate) \
25 (((tristate) >= PMUX_TRI_NORMAL) && ((tristate) <= PMUX_TRI_TRISTATE))
27 #ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
28 /* return 1 if a pin_io_is in range */
29 #define pmux_pin_io_isvalid(io) \
30 (((io) >= PMUX_PIN_OUTPUT) && ((io) <= PMUX_PIN_INPUT))
33 #ifdef TEGRA_PMX_PINS_HAVE_LOCK
34 /* return 1 if a pin_lock is in range */
35 #define pmux_pin_lock_isvalid(lock) \
36 (((lock) >= PMUX_PIN_LOCK_DISABLE) && ((lock) <= PMUX_PIN_LOCK_ENABLE))
39 #ifdef TEGRA_PMX_PINS_HAVE_OD
40 /* return 1 if a pin_od is in range */
41 #define pmux_pin_od_isvalid(od) \
42 (((od) >= PMUX_PIN_OD_DISABLE) && ((od) <= PMUX_PIN_OD_ENABLE))
45 #ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
46 /* return 1 if a pin_ioreset_is in range */
47 #define pmux_pin_ioreset_isvalid(ioreset) \
48 (((ioreset) >= PMUX_PIN_IO_RESET_DISABLE) && \
49 ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
52 #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
53 /* return 1 if a pin_rcv_sel_is in range */
54 #define pmux_pin_rcv_sel_isvalid(rcv_sel) \
55 (((rcv_sel) >= PMUX_PIN_RCV_SEL_NORMAL) && \
56 ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
59 #ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
60 /* return 1 if a pin_e_io_hv is in range */
61 #define pmux_pin_e_io_hv_isvalid(e_io_hv) \
62 (((e_io_hv) >= PMUX_PIN_E_IO_HV_NORMAL) && \
63 ((e_io_hv) <= PMUX_PIN_E_IO_HV_HIGH))
66 #ifdef TEGRA_PMX_GRPS_HAVE_LPMD
67 #define pmux_lpmd_isvalid(lpm) \
68 (((lpm) >= PMUX_LPMD_X8) && ((lpm) <= PMUX_LPMD_X))
71 #if defined(TEGRA_PMX_PINS_HAVE_SCHMT) || defined(TEGRA_PMX_GRPS_HAVE_SCHMT)
72 #define pmux_schmt_isvalid(schmt) \
73 (((schmt) >= PMUX_SCHMT_DISABLE) && ((schmt) <= PMUX_SCHMT_ENABLE))
76 #if defined(TEGRA_PMX_PINS_HAVE_HSM) || defined(TEGRA_PMX_GRPS_HAVE_HSM)
77 #define pmux_hsm_isvalid(hsm) \
78 (((hsm) >= PMUX_HSM_DISABLE) && ((hsm) <= PMUX_HSM_ENABLE))
81 #define _R(offset) (u32 *)(NV_PA_APB_MISC_BASE + (offset))
83 #if defined(CONFIG_TEGRA20)
85 #define MUX_REG(grp) _R(0x80 + ((tegra_soc_pingroups[grp].ctl_id / 16) * 4))
86 #define MUX_SHIFT(grp) ((tegra_soc_pingroups[grp].ctl_id % 16) * 2)
88 #define PULL_REG(grp) _R(0xa0 + ((tegra_soc_pingroups[grp].pull_id / 16) * 4))
89 #define PULL_SHIFT(grp) ((tegra_soc_pingroups[grp].pull_id % 16) * 2)
91 #define TRI_REG(grp) _R(0x14 + (((grp) / 32) * 4))
92 #define TRI_SHIFT(grp) ((grp) % 32)
96 #define REG(pin) _R(0x3000 + ((pin) * 4))
98 #define MUX_REG(pin) REG(pin)
99 #define MUX_SHIFT(pin) 0
101 #define PULL_REG(pin) REG(pin)
102 #define PULL_SHIFT(pin) 2
104 #define TRI_REG(pin) REG(pin)
105 #define TRI_SHIFT(pin) 4
107 #endif /* CONFIG_TEGRA20 */
109 #define DRV_REG(group) _R(TEGRA_PMX_SOC_DRV_GROUP_BASE_REG + ((group) * 4))
112 * We could force arch-tegraNN/pinmux.h to define all of these. However,
113 * that's a lot of defines, and for now it's manageable to just put a
114 * special case here. It's possible this decision will change with future
117 #ifdef CONFIG_TEGRA210
120 #ifdef TEGRA_PMX_PINS_HAVE_HSM
123 #define E_IO_HV_SHIFT 10
125 #ifdef TEGRA_PMX_PINS_HAVE_SCHMT
126 #define SCHMT_SHIFT 12
132 #define IO_RESET_SHIFT 8
133 #define RCV_SEL_SHIFT 9
136 #ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING
137 /* This register/field only exists on Tegra114 and later */
138 #define APB_MISC_PP_PINMUX_GLOBAL_0 0x40
139 #define CLAMP_INPUTS_WHEN_TRISTATED 1
141 void pinmux_set_tristate_input_clamping(void)
143 u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0);
145 setbits_le32(reg, CLAMP_INPUTS_WHEN_TRISTATED);
148 void pinmux_clear_tristate_input_clamping(void)
150 u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0);
152 clrbits_le32(reg, CLAMP_INPUTS_WHEN_TRISTATED);
156 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
158 u32 *reg = MUX_REG(pin);
162 if (func == PMUX_FUNC_DEFAULT)
165 /* Error check on pin and func */
166 assert(pmux_pingrp_isvalid(pin));
167 assert(pmux_func_isvalid(func));
169 if (func >= PMUX_FUNC_RSVD1) {
170 mux = (func - PMUX_FUNC_RSVD1) & 3;
172 /* Search for the appropriate function */
173 for (i = 0; i < 4; i++) {
174 if (tegra_soc_pingroups[pin].funcs[i] == func) {
183 val &= ~(3 << MUX_SHIFT(pin));
184 val |= (mux << MUX_SHIFT(pin));
188 void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
190 u32 *reg = PULL_REG(pin);
193 /* Error check on pin and pupd */
194 assert(pmux_pingrp_isvalid(pin));
195 assert(pmux_pin_pupd_isvalid(pupd));
198 val &= ~(3 << PULL_SHIFT(pin));
199 val |= (pupd << PULL_SHIFT(pin));
203 static void pinmux_set_tristate(enum pmux_pingrp pin, int tri)
205 u32 *reg = TRI_REG(pin);
208 /* Error check on pin */
209 assert(pmux_pingrp_isvalid(pin));
210 assert(pmux_pin_tristate_isvalid(tri));
213 if (tri == PMUX_TRI_TRISTATE)
214 val |= (1 << TRI_SHIFT(pin));
216 val &= ~(1 << TRI_SHIFT(pin));
220 void pinmux_tristate_enable(enum pmux_pingrp pin)
222 pinmux_set_tristate(pin, PMUX_TRI_TRISTATE);
225 void pinmux_tristate_disable(enum pmux_pingrp pin)
227 pinmux_set_tristate(pin, PMUX_TRI_NORMAL);
230 #ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
231 void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
236 if (io == PMUX_PIN_NONE)
239 /* Error check on pin and io */
240 assert(pmux_pingrp_isvalid(pin));
241 assert(pmux_pin_io_isvalid(io));
244 if (io == PMUX_PIN_INPUT)
245 val |= (io & 1) << IO_SHIFT;
247 val &= ~(1 << IO_SHIFT);
252 #ifdef TEGRA_PMX_PINS_HAVE_LOCK
253 static void pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
258 if (lock == PMUX_PIN_LOCK_DEFAULT)
261 /* Error check on pin and lock */
262 assert(pmux_pingrp_isvalid(pin));
263 assert(pmux_pin_lock_isvalid(lock));
266 if (lock == PMUX_PIN_LOCK_ENABLE) {
267 val |= (1 << LOCK_SHIFT);
269 if (val & (1 << LOCK_SHIFT))
270 printf("%s: Cannot clear LOCK bit!\n", __func__);
271 val &= ~(1 << LOCK_SHIFT);
279 #ifdef TEGRA_PMX_PINS_HAVE_OD
280 static void pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
285 if (od == PMUX_PIN_OD_DEFAULT)
288 /* Error check on pin and od */
289 assert(pmux_pingrp_isvalid(pin));
290 assert(pmux_pin_od_isvalid(od));
293 if (od == PMUX_PIN_OD_ENABLE)
294 val |= (1 << OD_SHIFT);
296 val &= ~(1 << OD_SHIFT);
303 #ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
304 static void pinmux_set_ioreset(enum pmux_pingrp pin,
305 enum pmux_pin_ioreset ioreset)
310 if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
313 /* Error check on pin and ioreset */
314 assert(pmux_pingrp_isvalid(pin));
315 assert(pmux_pin_ioreset_isvalid(ioreset));
318 if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
319 val |= (1 << IO_RESET_SHIFT);
321 val &= ~(1 << IO_RESET_SHIFT);
328 #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
329 static void pinmux_set_rcv_sel(enum pmux_pingrp pin,
330 enum pmux_pin_rcv_sel rcv_sel)
335 if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT)
338 /* Error check on pin and rcv_sel */
339 assert(pmux_pingrp_isvalid(pin));
340 assert(pmux_pin_rcv_sel_isvalid(rcv_sel));
343 if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH)
344 val |= (1 << RCV_SEL_SHIFT);
346 val &= ~(1 << RCV_SEL_SHIFT);
353 #ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
354 static void pinmux_set_e_io_hv(enum pmux_pingrp pin,
355 enum pmux_pin_e_io_hv e_io_hv)
360 if (e_io_hv == PMUX_PIN_E_IO_HV_DEFAULT)
363 /* Error check on pin and e_io_hv */
364 assert(pmux_pingrp_isvalid(pin));
365 assert(pmux_pin_e_io_hv_isvalid(e_io_hv));
368 if (e_io_hv == PMUX_PIN_E_IO_HV_HIGH)
369 val |= (1 << E_IO_HV_SHIFT);
371 val &= ~(1 << E_IO_HV_SHIFT);
378 #ifdef TEGRA_PMX_PINS_HAVE_SCHMT
379 static void pinmux_set_schmt(enum pmux_pingrp pin, enum pmux_schmt schmt)
384 /* NONE means unspecified/do not change/use POR value */
385 if (schmt == PMUX_SCHMT_NONE)
388 /* Error check pad */
389 assert(pmux_pingrp_isvalid(pin));
390 assert(pmux_schmt_isvalid(schmt));
393 if (schmt == PMUX_SCHMT_ENABLE)
394 val |= (1 << SCHMT_SHIFT);
396 val &= ~(1 << SCHMT_SHIFT);
403 #ifdef TEGRA_PMX_PINS_HAVE_HSM
404 static void pinmux_set_hsm(enum pmux_pingrp pin, enum pmux_hsm hsm)
409 /* NONE means unspecified/do not change/use POR value */
410 if (hsm == PMUX_HSM_NONE)
413 /* Error check pad */
414 assert(pmux_pingrp_isvalid(pin));
415 assert(pmux_hsm_isvalid(hsm));
418 if (hsm == PMUX_HSM_ENABLE)
419 val |= (1 << HSM_SHIFT);
421 val &= ~(1 << HSM_SHIFT);
428 static void pinmux_config_pingrp(const struct pmux_pingrp_config *config)
430 enum pmux_pingrp pin = config->pingrp;
432 pinmux_set_func(pin, config->func);
433 pinmux_set_pullupdown(pin, config->pull);
434 pinmux_set_tristate(pin, config->tristate);
435 #ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
436 pinmux_set_io(pin, config->io);
438 #ifdef TEGRA_PMX_PINS_HAVE_LOCK
439 pinmux_set_lock(pin, config->lock);
441 #ifdef TEGRA_PMX_PINS_HAVE_OD
442 pinmux_set_od(pin, config->od);
444 #ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
445 pinmux_set_ioreset(pin, config->ioreset);
447 #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
448 pinmux_set_rcv_sel(pin, config->rcv_sel);
450 #ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
451 pinmux_set_e_io_hv(pin, config->e_io_hv);
453 #ifdef TEGRA_PMX_PINS_HAVE_SCHMT
454 pinmux_set_schmt(pin, config->schmt);
456 #ifdef TEGRA_PMX_PINS_HAVE_HSM
457 pinmux_set_hsm(pin, config->hsm);
461 void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
466 for (i = 0; i < len; i++)
467 pinmux_config_pingrp(&config[i]);
470 #ifdef TEGRA_PMX_SOC_HAS_DRVGRPS
472 #define pmux_drvgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PMUX_DRVGRP_COUNT))
474 #define pmux_slw_isvalid(slw) \
475 (((slw) >= PMUX_SLWF_MIN) && ((slw) <= PMUX_SLWF_MAX))
477 #define pmux_drv_isvalid(drv) \
478 (((drv) >= PMUX_DRVUP_MIN) && ((drv) <= PMUX_DRVUP_MAX))
480 #ifdef TEGRA_PMX_GRPS_HAVE_HSM
483 #ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
484 #define SCHMT_SHIFT 3
486 #ifdef TEGRA_PMX_GRPS_HAVE_LPMD
488 #define LPMD_MASK (3 << LPMD_SHIFT)
491 * Note that the following DRV* and SLW* defines are accurate for many drive
492 * groups on many SoCs. We really need a per-group data structure to solve
493 * this, since the fields are in different positions/sizes in different
494 * registers (for different groups).
496 * On Tegra30/114/124, the DRV*_SHIFT values vary.
497 * On Tegra30, the SLW*_SHIFT values vary.
498 * On Tegra30/114/124/210, the DRV*_MASK values vary, although the values
499 * below are wide enough to cover the widest fields, and hopefully don't
500 * interfere with any other fields.
501 * On Tegra30, the SLW*_MASK values vary, but we can't use a value that's
502 * wide enough to cover all cases, since that would cause the field to
503 * overlap with other fields in the narrower cases.
505 #define DRVDN_SHIFT 12
506 #define DRVDN_MASK (0x7F << DRVDN_SHIFT)
507 #define DRVUP_SHIFT 20
508 #define DRVUP_MASK (0x7F << DRVUP_SHIFT)
509 #define SLWR_SHIFT 28
510 #define SLWR_MASK (3 << SLWR_SHIFT)
511 #define SLWF_SHIFT 30
512 #define SLWF_MASK (3 << SLWF_SHIFT)
514 static void pinmux_set_drvup_slwf(enum pmux_drvgrp grp, int slwf)
516 u32 *reg = DRV_REG(grp);
519 /* NONE means unspecified/do not change/use POR value */
520 if (slwf == PMUX_SLWF_NONE)
523 /* Error check on pad and slwf */
524 assert(pmux_drvgrp_isvalid(grp));
525 assert(pmux_slw_isvalid(slwf));
529 val |= (slwf << SLWF_SHIFT);
535 static void pinmux_set_drvdn_slwr(enum pmux_drvgrp grp, int slwr)
537 u32 *reg = DRV_REG(grp);
540 /* NONE means unspecified/do not change/use POR value */
541 if (slwr == PMUX_SLWR_NONE)
544 /* Error check on pad and slwr */
545 assert(pmux_drvgrp_isvalid(grp));
546 assert(pmux_slw_isvalid(slwr));
550 val |= (slwr << SLWR_SHIFT);
556 static void pinmux_set_drvup(enum pmux_drvgrp grp, int drvup)
558 u32 *reg = DRV_REG(grp);
561 /* NONE means unspecified/do not change/use POR value */
562 if (drvup == PMUX_DRVUP_NONE)
565 /* Error check on pad and drvup */
566 assert(pmux_drvgrp_isvalid(grp));
567 assert(pmux_drv_isvalid(drvup));
571 val |= (drvup << DRVUP_SHIFT);
577 static void pinmux_set_drvdn(enum pmux_drvgrp grp, int drvdn)
579 u32 *reg = DRV_REG(grp);
582 /* NONE means unspecified/do not change/use POR value */
583 if (drvdn == PMUX_DRVDN_NONE)
586 /* Error check on pad and drvdn */
587 assert(pmux_drvgrp_isvalid(grp));
588 assert(pmux_drv_isvalid(drvdn));
592 val |= (drvdn << DRVDN_SHIFT);
598 #ifdef TEGRA_PMX_GRPS_HAVE_LPMD
599 static void pinmux_set_lpmd(enum pmux_drvgrp grp, enum pmux_lpmd lpmd)
601 u32 *reg = DRV_REG(grp);
604 /* NONE means unspecified/do not change/use POR value */
605 if (lpmd == PMUX_LPMD_NONE)
608 /* Error check pad and lpmd value */
609 assert(pmux_drvgrp_isvalid(grp));
610 assert(pmux_lpmd_isvalid(lpmd));
614 val |= (lpmd << LPMD_SHIFT);
621 #ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
622 static void pinmux_set_schmt(enum pmux_drvgrp grp, enum pmux_schmt schmt)
624 u32 *reg = DRV_REG(grp);
627 /* NONE means unspecified/do not change/use POR value */
628 if (schmt == PMUX_SCHMT_NONE)
631 /* Error check pad */
632 assert(pmux_drvgrp_isvalid(grp));
633 assert(pmux_schmt_isvalid(schmt));
636 if (schmt == PMUX_SCHMT_ENABLE)
637 val |= (1 << SCHMT_SHIFT);
639 val &= ~(1 << SCHMT_SHIFT);
646 #ifdef TEGRA_PMX_GRPS_HAVE_HSM
647 static void pinmux_set_hsm(enum pmux_drvgrp grp, enum pmux_hsm hsm)
649 u32 *reg = DRV_REG(grp);
652 /* NONE means unspecified/do not change/use POR value */
653 if (hsm == PMUX_HSM_NONE)
656 /* Error check pad */
657 assert(pmux_drvgrp_isvalid(grp));
658 assert(pmux_hsm_isvalid(hsm));
661 if (hsm == PMUX_HSM_ENABLE)
662 val |= (1 << HSM_SHIFT);
664 val &= ~(1 << HSM_SHIFT);
671 static void pinmux_config_drvgrp(const struct pmux_drvgrp_config *config)
673 enum pmux_drvgrp grp = config->drvgrp;
675 pinmux_set_drvup_slwf(grp, config->slwf);
676 pinmux_set_drvdn_slwr(grp, config->slwr);
677 pinmux_set_drvup(grp, config->drvup);
678 pinmux_set_drvdn(grp, config->drvdn);
679 #ifdef TEGRA_PMX_GRPS_HAVE_LPMD
680 pinmux_set_lpmd(grp, config->lpmd);
682 #ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
683 pinmux_set_schmt(grp, config->schmt);
685 #ifdef TEGRA_PMX_GRPS_HAVE_HSM
686 pinmux_set_hsm(grp, config->hsm);
690 void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
695 for (i = 0; i < len; i++)
696 pinmux_config_drvgrp(&config[i]);
698 #endif /* TEGRA_PMX_HAS_DRVGRPS */