2 * Copyright (c) 2011 The Chromium OS Authors.
3 * (C) Copyright 2010-2015
4 * NVIDIA Corporation <www.nvidia.com>
6 * SPDX-License-Identifier: GPL-2.0+
9 /* Tegra20 Clock control functions */
14 #include <asm/arch/clock.h>
15 #include <asm/arch/tegra.h>
16 #include <asm/arch-tegra/clk_rst.h>
17 #include <asm/arch-tegra/timer.h>
22 * Clock types that we can use as a source. The Tegra20 has muxes for the
23 * peripheral clocks, and in most cases there are four options for the clock
24 * source. This gives us a clock 'type' and exploits what commonality exists
27 * Letters are obvious, except for T which means CLK_M, and S which means the
28 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
29 * datasheet) and PLL_M are different things. The former is the basic
30 * clock supplied to the SOC from an external oscillator. The latter is the
33 * See definitions in clock_id in the header file.
36 CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
37 CLOCK_TYPE_MCPA, /* and so on */
41 CLOCK_TYPE_PCMT16, /* CLOCK_TYPE_PCMT with 16-bit divider */
46 CLOCK_TYPE_NONE = -1, /* invalid clock type */
50 CLOCK_MAX_MUX = 4 /* number of source options for each clock */
54 * Clock source mux for each clock type. This just converts our enum into
55 * a list of mux sources for use by the code. Note that CLOCK_TYPE_PCXTS
56 * is special as it has 5 sources. Since it also has a different number of
57 * bits in its register for the source, we just handle it with a special
60 #define CLK(x) CLOCK_ID_ ## x
61 static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX] = {
62 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC) },
63 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO) },
64 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC) },
65 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE) },
66 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) },
67 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) },
68 { CLK(PERIPH), CLK(CGENERAL), CLK(XCPU), CLK(OSC) },
69 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC) },
73 * Clock peripheral IDs which sadly don't match up with PERIPH_ID. This is
74 * not in the header file since it is for purely internal use - we want
75 * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
76 * confusion bewteen PERIPH_ID_... and PERIPHC_...
78 * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
81 * Note to SOC vendors: perhaps define a unified numbering for peripherals and
82 * use it for reset, clock enable, clock source/divider and even pinmuxing
85 enum periphc_internal_id {
102 PERIPHC_10, /* PERIPHC_SPI1, what is this really? */
160 * Clock type for each peripheral clock source. We put the name in each
161 * record just so it is easy to match things up
163 #define TYPE(name, type) type
164 static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
166 TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
167 TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
168 TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
169 TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM),
170 TYPE(PERIPHC_PWM, CLOCK_TYPE_PCXTS),
171 TYPE(PERIPHC_SPI1, CLOCK_TYPE_PCMT),
172 TYPE(PERIPHC_SPI22, CLOCK_TYPE_PCMT),
173 TYPE(PERIPHC_SPI3, CLOCK_TYPE_PCMT),
176 TYPE(PERIPHC_XIO, CLOCK_TYPE_PCMT),
177 TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16),
178 TYPE(PERIPHC_DVC_I2C, CLOCK_TYPE_PCMT16),
179 TYPE(PERIPHC_TWC, CLOCK_TYPE_PCMT),
180 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
181 TYPE(PERIPHC_SPI1, CLOCK_TYPE_PCMT),
182 TYPE(PERIPHC_DISP1, CLOCK_TYPE_PDCT),
183 TYPE(PERIPHC_DISP2, CLOCK_TYPE_PDCT),
186 TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT),
187 TYPE(PERIPHC_IDE0, CLOCK_TYPE_PCMT),
188 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
189 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
190 TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT),
191 TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PCMT),
192 TYPE(PERIPHC_G3D, CLOCK_TYPE_MCPA),
193 TYPE(PERIPHC_G2D, CLOCK_TYPE_MCPA),
196 TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PCMT),
197 TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PCMT),
198 TYPE(PERIPHC_VFIR, CLOCK_TYPE_PCMT),
199 TYPE(PERIPHC_EPP, CLOCK_TYPE_MCPA),
200 TYPE(PERIPHC_MPE, CLOCK_TYPE_MCPA),
201 TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT),
202 TYPE(PERIPHC_UART1, CLOCK_TYPE_PCMT),
203 TYPE(PERIPHC_UART2, CLOCK_TYPE_PCMT),
206 TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA),
207 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
208 TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT),
209 TYPE(PERIPHC_HDMI, CLOCK_TYPE_PDCT),
210 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
211 TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT),
212 TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16),
213 TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT),
216 TYPE(PERIPHC_UART3, CLOCK_TYPE_PCMT),
217 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
218 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
219 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
220 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
221 TYPE(PERIPHC_SPI4, CLOCK_TYPE_PCMT),
222 TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16),
223 TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT),
226 TYPE(PERIPHC_UART4, CLOCK_TYPE_PCMT),
227 TYPE(PERIPHC_UART5, CLOCK_TYPE_PCMT),
228 TYPE(PERIPHC_VDE, CLOCK_TYPE_PCMT),
229 TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT),
230 TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT),
231 TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT),
235 * This array translates a periph_id to a periphc_internal_id
237 * Not present/matched up:
238 * uint vi_sensor; _VI_SENSOR_0, 0x1A8
239 * SPDIF - which is both 0x08 and 0x0c
242 #define NONE(name) (-1)
243 #define OFFSET(name, value) PERIPHC_ ## name
244 static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
253 PERIPHC_UART2, /* and vfir 0x68 */
258 NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */
285 /* Middle word: 63:32 */
297 NONE(SBC1), /* SBC1, 0x34, is this SPI1? */
307 PERIPHC_TVO, /* also CVE 0x40 */
325 /* Upper word 95:64 */
360 * PLL divider shift/mask tables for all PLL IDs.
362 struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
365 * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLX, etc.)
366 * If lock_ena or lock_det are >31, they're not used in that PLL.
369 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x0F,
370 .lock_ena = 24, .lock_det = 27, .kcp_shift = 28, .kcp_mask = 3, .kvco_shift = 27, .kvco_mask = 1 }, /* PLLC */
371 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 0, .p_mask = 0,
372 .lock_ena = 0, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLM */
373 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
374 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLP */
375 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
376 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLA */
377 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x01,
378 .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLU */
379 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
380 .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD */
381 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x0F,
382 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLX */
383 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
384 .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */
385 { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
386 .lock_ena = 18, .lock_det = 0, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS */
390 * Get the oscillator frequency, from the corresponding hardware configuration
391 * field. T20 has 4 frequencies that it supports.
393 enum clock_osc_freq clock_get_osc_freq(void)
395 struct clk_rst_ctlr *clkrst =
396 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
399 reg = readl(&clkrst->crc_osc_ctrl);
400 return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
403 /* Returns a pointer to the clock source register for a peripheral */
404 u32 *get_periph_source_reg(enum periph_id periph_id)
406 struct clk_rst_ctlr *clkrst =
407 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
408 enum periphc_internal_id internal_id;
410 assert(clock_periph_id_isvalid(periph_id));
411 internal_id = periph_id_to_internal_id[periph_id];
412 assert(internal_id != -1);
413 return &clkrst->crc_clk_src[internal_id];
417 * Given a peripheral ID and the required source clock, this returns which
418 * value should be programmed into the source mux for that peripheral.
420 * There is special code here to handle the one source type with 5 sources.
422 * @param periph_id peripheral to start
423 * @param source PLL id of required parent clock
424 * @param mux_bits Set to number of bits in mux register: 2 or 4
425 * @param divider_bits Set to number of divider bits (8 or 16)
426 * @return mux value (0-4, or -1 if not found)
428 int get_periph_clock_source(enum periph_id periph_id,
429 enum clock_id parent, int *mux_bits, int *divider_bits)
431 enum clock_type_id type;
432 enum periphc_internal_id internal_id;
435 assert(clock_periph_id_isvalid(periph_id));
437 internal_id = periph_id_to_internal_id[periph_id];
438 assert(periphc_internal_id_isvalid(internal_id));
440 type = clock_periph_type[internal_id];
441 assert(clock_type_id_isvalid(type));
444 * Special cases here for the clock with a 4-bit source mux and I2C
445 * with its 16-bit divisor
447 if (type == CLOCK_TYPE_PCXTS)
448 *mux_bits = MASK_BITS_31_28;
450 *mux_bits = MASK_BITS_31_30;
451 if (type == CLOCK_TYPE_PCMT16)
456 for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
457 if (clock_source[type][mux] == parent)
461 * Not found: it might be looking for the 'S' in CLOCK_TYPE_PCXTS
462 * which is not in our table. If not, then they are asking for a
463 * source which this peripheral can't access through its mux.
465 assert(type == CLOCK_TYPE_PCXTS);
466 assert(parent == CLOCK_ID_SFROM32KHZ);
467 if (type == CLOCK_TYPE_PCXTS && parent == CLOCK_ID_SFROM32KHZ)
468 return 4; /* mux value for this clock */
470 /* if we get here, either us or the caller has made a mistake */
471 printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
476 void clock_set_enable(enum periph_id periph_id, int enable)
478 struct clk_rst_ctlr *clkrst =
479 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
480 u32 *clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
483 /* Enable/disable the clock to this peripheral */
484 assert(clock_periph_id_isvalid(periph_id));
487 reg |= PERIPH_MASK(periph_id);
489 reg &= ~PERIPH_MASK(periph_id);
493 void reset_set_enable(enum periph_id periph_id, int enable)
495 struct clk_rst_ctlr *clkrst =
496 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
497 u32 *reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
500 /* Enable/disable reset to the peripheral */
501 assert(clock_periph_id_isvalid(periph_id));
504 reg |= PERIPH_MASK(periph_id);
506 reg &= ~PERIPH_MASK(periph_id);
510 #if CONFIG_IS_ENABLED(OF_CONTROL)
512 * Convert a device tree clock ID to our peripheral ID. They are mostly
513 * the same but we are very cautious so we check that a valid clock ID is
516 * @param clk_id Clock ID according to tegra20 device tree binding
517 * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
519 enum periph_id clk_id_to_periph_id(int clk_id)
521 if (clk_id > PERIPH_ID_COUNT)
522 return PERIPH_ID_NONE;
525 case PERIPH_ID_RESERVED1:
526 case PERIPH_ID_RESERVED2:
527 case PERIPH_ID_RESERVED30:
528 case PERIPH_ID_RESERVED35:
529 case PERIPH_ID_RESERVED56:
530 case PERIPH_ID_PCIEXCLK:
531 case PERIPH_ID_RESERVED76:
532 case PERIPH_ID_RESERVED77:
533 case PERIPH_ID_RESERVED78:
534 case PERIPH_ID_RESERVED79:
535 case PERIPH_ID_RESERVED80:
536 case PERIPH_ID_RESERVED81:
537 case PERIPH_ID_RESERVED82:
538 case PERIPH_ID_RESERVED83:
539 case PERIPH_ID_RESERVED91:
540 return PERIPH_ID_NONE;
545 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
547 void clock_early_init(void)
550 * PLLP output frequency set to 216MHz
551 * PLLC output frequency set to 600Mhz
553 * TODO: Can we calculate these values instead of hard-coding?
555 switch (clock_get_osc_freq()) {
556 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
557 clock_set_rate(CLOCK_ID_PERIPH, 432, 12, 1, 8);
558 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
561 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
562 clock_set_rate(CLOCK_ID_PERIPH, 432, 26, 1, 8);
563 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
566 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
567 clock_set_rate(CLOCK_ID_PERIPH, 432, 13, 1, 8);
568 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
570 case CLOCK_OSC_FREQ_19_2:
573 * These are not supported. It is too early to print a
574 * message and the UART likely won't work anyway due to the
575 * oscillator being wrong.
581 void arch_timer_init(void)
585 #define PMC_SATA_PWRGT 0x1ac
586 #define PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE (1 << 5)
587 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1 << 4)
589 #define PLLE_SS_CNTL 0x68
590 #define PLLE_SS_CNTL_SSCINCINTRV(x) (((x) & 0x3f) << 24)
591 #define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16)
592 #define PLLE_SS_CNTL_SSCBYP (1 << 12)
593 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11)
594 #define PLLE_SS_CNTL_BYPASS_SS (1 << 10)
595 #define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0)
597 #define PLLE_BASE 0x0e8
598 #define PLLE_BASE_ENABLE_CML (1 << 31)
599 #define PLLE_BASE_ENABLE (1 << 30)
600 #define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24)
601 #define PLLE_BASE_PLDIV(x) (((x) & 0x3f) << 16)
602 #define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8)
603 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0)
605 #define PLLE_MISC 0x0ec
606 #define PLLE_MISC_SETUP_BASE(x) (((x) & 0xffff) << 16)
607 #define PLLE_MISC_PLL_READY (1 << 15)
608 #define PLLE_MISC_LOCK (1 << 11)
609 #define PLLE_MISC_LOCK_ENABLE (1 << 9)
610 #define PLLE_MISC_SETUP_EXT(x) (((x) & 0x3) << 2)
612 static int tegra_plle_train(void)
614 unsigned int timeout = 2000;
617 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
618 value |= PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE;
619 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
621 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
622 value |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
623 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
625 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
626 value &= ~PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE;
627 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
630 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
631 if (value & PLLE_MISC_PLL_READY)
638 error("timeout waiting for PLLE to become ready");
645 int tegra_plle_enable(void)
647 unsigned int timeout = 1000;
651 /* disable PLLE clock */
652 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
653 value &= ~PLLE_BASE_ENABLE_CML;
654 value &= ~PLLE_BASE_ENABLE;
655 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
657 /* clear lock enable and setup field */
658 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
659 value &= ~PLLE_MISC_LOCK_ENABLE;
660 value &= ~PLLE_MISC_SETUP_BASE(0xffff);
661 value &= ~PLLE_MISC_SETUP_EXT(0x3);
662 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
664 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
665 if ((value & PLLE_MISC_PLL_READY) == 0) {
666 err = tegra_plle_train();
668 error("failed to train PLLE: %d", err);
673 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
674 value |= PLLE_MISC_SETUP_BASE(0x7);
675 value |= PLLE_MISC_LOCK_ENABLE;
676 value |= PLLE_MISC_SETUP_EXT(0);
677 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
679 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
680 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET |
681 PLLE_SS_CNTL_BYPASS_SS;
682 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
684 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
685 value |= PLLE_BASE_ENABLE_CML | PLLE_BASE_ENABLE;
686 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
689 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
690 if (value & PLLE_MISC_LOCK)
697 error("timeout waiting for PLLE to lock");
703 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
704 value &= ~PLLE_SS_CNTL_SSCINCINTRV(0x3f);
705 value |= PLLE_SS_CNTL_SSCINCINTRV(0x18);
707 value &= ~PLLE_SS_CNTL_SSCINC(0xff);
708 value |= PLLE_SS_CNTL_SSCINC(0x01);
710 value &= ~PLLE_SS_CNTL_SSCBYP;
711 value &= ~PLLE_SS_CNTL_INTERP_RESET;
712 value &= ~PLLE_SS_CNTL_BYPASS_SS;
714 value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff);
715 value |= PLLE_SS_CNTL_SSCMAX(0x24);
716 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);