2 * Copyright (C) 2014 Panasonic Corporation
3 * Copyright (C) 2015-2016 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/sizes.h>
13 #include "../soc-info.h"
14 #include "ddrphy-regs.h"
16 /* Select either decimal or hexadecimal */
18 #define PRINTF_FORMAT "%2d"
20 #define PRINTF_FORMAT "%02x"
25 #define ptr_to_uint(p) ((unsigned int)(unsigned long)(p))
32 static const struct phy_param uniphier_ld4_phy_param[] = {
33 { .base = 0x5bc01000, .nr_dx = 2, },
34 { .base = 0x5be01000, .nr_dx = 2, },
38 static const struct phy_param uniphier_pro4_phy_param[] = {
39 { .base = 0x5bc01000, .nr_dx = 2, },
40 { .base = 0x5bc02000, .nr_dx = 2, },
41 { .base = 0x5be01000, .nr_dx = 2, },
42 { .base = 0x5be02000, .nr_dx = 2, },
46 static const struct phy_param uniphier_sld8_phy_param[] = {
47 { .base = 0x5bc01000, .nr_dx = 2, },
48 { .base = 0x5be01000, .nr_dx = 2, },
52 static const struct phy_param uniphier_ld11_phy_param[] = {
53 { .base = 0x5bc01000, .nr_dx = 4, },
57 static void print_bdl(void __iomem *reg, int n)
62 for (i = 0; i < n; i++)
63 printf(FS PRINTF_FORMAT, (val >> i * 6) & 0x3f);
66 static void dump_loop(const struct phy_param *phy_param,
67 void (*callback)(void __iomem *))
69 void __iomem *phy_base, *dx_base;
72 for (p = 0; phy_param->base; phy_param++, p++) {
73 phy_base = ioremap(phy_param->base, SZ_4K);
74 dx_base = phy_base + PHY_DX_BASE;
76 for (dx = 0; dx < phy_param->nr_dx; dx++) {
77 printf("PHY%dDX%d:", p, dx);
79 dx_base += PHY_DX_STRIDE;
87 static void __wbdl_dump(void __iomem *dx_base)
89 print_bdl(dx_base + PHY_DX_BDLR0, 5);
90 print_bdl(dx_base + PHY_DX_BDLR1, 5);
92 printf(FS "(+" PRINTF_FORMAT ")",
93 readl(dx_base + PHY_DX_LCDLR1) & 0xff);
96 static void wbdl_dump(const struct phy_param *phy_param)
98 printf("\n--- Write Bit Delay Line ---\n");
99 printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n");
101 dump_loop(phy_param, &__wbdl_dump);
104 static void __rbdl_dump(void __iomem *dx_base)
106 print_bdl(dx_base + PHY_DX_BDLR3, 5);
107 print_bdl(dx_base + PHY_DX_BDLR4, 4);
109 printf(FS "(+" PRINTF_FORMAT ")",
110 (readl(dx_base + PHY_DX_LCDLR1) >> 8) & 0xff);
113 static void rbdl_dump(const struct phy_param *phy_param)
115 printf("\n--- Read Bit Delay Line ---\n");
116 printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD)\n");
118 dump_loop(phy_param, &__rbdl_dump);
121 static void __wld_dump(void __iomem *dx_base)
124 u32 lcdlr0 = readl(dx_base + PHY_DX_LCDLR0);
125 u32 gtr = readl(dx_base + PHY_DX_GTR);
127 for (rank = 0; rank < 4; rank++) {
128 u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */
129 u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */
131 printf(FS PRINTF_FORMAT "%sT", wld,
132 wlsl == 0 ? "-1" : wlsl == 1 ? "+0" : "+1");
136 static void wld_dump(const struct phy_param *phy_param)
138 printf("\n--- Write Leveling Delay ---\n");
139 printf(" Rank0 Rank1 Rank2 Rank3\n");
141 dump_loop(phy_param, &__wld_dump);
144 static void __dqsgd_dump(void __iomem *dx_base)
147 u32 lcdlr2 = readl(dx_base + PHY_DX_LCDLR2);
148 u32 gtr = readl(dx_base + PHY_DX_GTR);
150 for (rank = 0; rank < 4; rank++) {
151 u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */
152 u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */
154 printf(FS PRINTF_FORMAT "+%dT", dqsgd, dgsl);
158 static void dqsgd_dump(const struct phy_param *phy_param)
160 printf("\n--- DQS Gating Delay ---\n");
161 printf(" Rank0 Rank1 Rank2 Rank3\n");
163 dump_loop(phy_param, &__dqsgd_dump);
166 static void __mdl_dump(void __iomem *dx_base)
169 u32 mdl = readl(dx_base + PHY_DX_MDLR);
170 for (i = 0; i < 3; i++)
171 printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
174 static void mdl_dump(const struct phy_param *phy_param)
176 printf("\n--- Master Delay Line ---\n");
177 printf(" IPRD TPRD MDLD\n");
179 dump_loop(phy_param, &__mdl_dump);
182 #define REG_DUMP(x) \
183 { int ofst = PHY_ ## x; void __iomem *reg = phy_base + ofst; \
184 printf("%3d: %-10s: %08x : %08x\n", \
185 ofst >> PHY_REG_SHIFT, #x, \
186 ptr_to_uint(reg), readl(reg)); }
188 #define DX_REG_DUMP(dx, x) \
189 { int ofst = PHY_DX_BASE + PHY_DX_STRIDE * (dx) + \
191 void __iomem *reg = phy_base + ofst; \
192 printf("%3d: DX%d%-7s: %08x : %08x\n", \
193 ofst >> PHY_REG_SHIFT, (dx), #x, \
194 ptr_to_uint(reg), readl(reg)); }
196 static void reg_dump(const struct phy_param *phy_param)
198 void __iomem *phy_base;
201 printf("\n--- DDR PHY registers ---\n");
203 for (p = 0; phy_param->base; phy_param++, p++) {
204 phy_base = ioremap(phy_param->base, SZ_4K);
206 printf("== PHY%d (base: %08x) ==\n", p, ptr_to_uint(phy_base));
207 printf(" No: Name : Address : Data\n");
234 for (dx = 0; dx < phy_param->nr_dx; dx++) {
235 DX_REG_DUMP(dx, GCR);
236 DX_REG_DUMP(dx, GTR);
243 static int do_ddr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
246 const struct phy_param *phy_param;
248 switch (uniphier_get_soc_type()) {
249 case SOC_UNIPHIER_LD4:
250 phy_param = uniphier_ld4_phy_param;
252 case SOC_UNIPHIER_PRO4:
253 phy_param = uniphier_pro4_phy_param;
255 case SOC_UNIPHIER_SLD8:
256 phy_param = uniphier_sld8_phy_param;
258 case SOC_UNIPHIER_LD11:
259 phy_param = uniphier_ld11_phy_param;
262 printf("unsupported SoC\n");
263 return CMD_RET_FAILURE;
269 if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
270 wbdl_dump(phy_param);
272 if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
273 rbdl_dump(phy_param);
275 if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
278 if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
279 dqsgd_dump(phy_param);
281 if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
284 if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
287 return CMD_RET_SUCCESS;
292 "UniPhier DDR PHY parameters dumper",
293 "- dump all of the following\n"
294 "ddr wbdl - dump Write Bit Delay\n"
295 "ddr rbdl - dump Read Bit Delay\n"
296 "ddr wld - dump Write Leveling\n"
297 "ddr dqsgd - dump DQS Gating Delay\n"
298 "ddr mdl - dump Master Delay Line\n"
299 "ddr reg - dump registers\n"