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   1 /*
   2  * Copyright (C) 2016 Socionext Inc.
   3  */
   4
   5 #ifndef _DDRPHY_LD20_REGS_H
   6 #define _DDRPHY_LD20_REGS_H
   7
   8 #define PHY_SCL_DATA_0                  0x00000104
   9 #define PHY_SCL_DATA_1                  0x00000108
  10 #define PHY_SCL_LATENCY                 0x0000010C
  11 #define PHY_SCL_START                   0x00000100
  12 #define PHY_SCL_CONFIG_1                0x00000118
  13 #define PHY_SCL_CONFIG_2                0x0000011C
  14 #define PHY_PAD_CTRL                    0x00000120
  15 #define PHY_DLL_RECALIB                 0x00000124
  16 #define PHY_DLL_ADRCTRL                 0x00000128
  17 #define PHY_LANE_SEL                    0x0000012C
  18 #define PHY_DLL_TRIM_1                  0x00000130
  19 #define PHY_DLL_TRIM_2                  0x00000134
  20 #define PHY_DLL_TRIM_3                  0x00000138
  21 #define PHY_SCL_MAIN_CLK_DELTA          0x00000140
  22 #define PHY_WRLVL_AUTOINC_TRIM          0x0000014C
  23 #define PHY_WRLVL_DYN_ODT               0x00000150
  24 #define PHY_WRLVL_ON_OFF                0x00000154
  25 #define PHY_UNQ_ANALOG_DLL_1            0x0000015C
  26 #define PHY_DLL_INCR_TRIM_1             0x00000164
  27 #define PHY_DLL_INCR_TRIM_3             0x00000168
  28 #define PHY_SCL_CONFIG_3                0x0000016C
  29 #define PHY_UNIQUIFY_TSMC_IO_1          0x00000170
  30 #define PHY_SCL_START_ADDR              0x00000188
  31 #define PHY_DSCL_CNT                    0x0000019C
  32 #define PHY_DLL_TRIM_CLK                0x000001A4
  33 #define PHY_DYNAMIC_BIT_LVL             0x000001AC
  34 #define PHY_SCL_WINDOW_TRIM             0x000001B4
  35 #define PHY_DISABLE_GATING_FOR_SCL      0x000001B8
  36 #define PHY_SCL_CONFIG_4                0x000001BC
  37 #define PHY_DYNAMIC_WRITE_BIT_LVL       0x000001C0
  38 #define PHY_VREF_TRAINING               0x000001C8
  39 #define PHY_SCL_GATE_TIMING             0x000001E0
  40
  41 #endif /* _DDRPHY_LD20_REGS_H */