git.sur5r.net Git - u-boot/blob - arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c

   1 /*
   2  * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <config.h>
   8 #include <linux/types.h>
   9 #include <linux/io.h>
  10
  11 #include "ddrphy-regs.h"
  12
  13 int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size,
  14                          bool ddr3plus)
  15 {
  16         u32 tmp;
  17
  18         writel(0x0300c473, &phy->pgcr[1]);
  19         if (freq == 1333) {
  20                 writel(0x0a806844, &phy->ptr[0]);
  21                 writel(0x208e0124, &phy->ptr[1]);
  22         } else {
  23                 writel(0x0c807d04, &phy->ptr[0]);
  24                 writel(0x2710015E, &phy->ptr[1]);
  25         }
  26         writel(0x00083DEF, &phy->ptr[2]);
  27         if (freq == 1333) {
  28                 writel(0x0f051616, &phy->ptr[3]);
  29                 writel(0x06ae08d6, &phy->ptr[4]);
  30         } else {
  31                 writel(0x12061A80, &phy->ptr[3]);
  32                 writel(0x08027100, &phy->ptr[4]);
  33         }
  34         writel(0xF004001A, &phy->dsgcr);
  35
  36         /* change the value of the on-die pull-up/pull-down registors */
  37         tmp = readl(&phy->dxccr);
  38         tmp &= ~0x0ee0;
  39         tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
  40         writel(tmp, &phy->dxccr);
  41
  42         writel(0x0000040B, &phy->dcr);
  43         if (freq == 1333) {
  44                 writel(0x85589955, &phy->dtpr[0]);
  45                 if (size == 1)
  46                         writel(0x1a8363c0, &phy->dtpr[1]);
  47                 else
  48                         writel(0x1a8363c0, &phy->dtpr[1]);
  49                 writel(0x5002c200, &phy->dtpr[2]);
  50                 writel(0x00000b51, &phy->mr0);
  51         } else {
  52                 writel(0x999cbb66, &phy->dtpr[0]);
  53                 if (size == 1)
  54                         writel(0x1a878400, &phy->dtpr[1]);
  55                 else
  56                         writel(0x1a878400, &phy->dtpr[1]);
  57                 writel(0xa00214f8, &phy->dtpr[2]);
  58                 writel(0x00000d71, &phy->mr0);
  59         }
  60         writel(0x00000006, &phy->mr1);
  61         if (freq == 1333)
  62                 writel(0x00000290, &phy->mr2);
  63         else
  64                 writel(0x00000298, &phy->mr2);
  65
  66         writel(ddr3plus ? 0x00000800 : 0x00000000, &phy->mr3);
  67
  68         while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
  69                 ;
  70
  71         writel(0x0300C473, &phy->pgcr[1]);
  72         writel(0x0000005D, &phy->zq[0].cr[1]);
  73
  74         return 0;
  75 }