2 * Copyright (C) 2011-2014 Panasonic Corporation
3 * Copyright (C) 2015-2016 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <linux/err.h>
12 #include <linux/sizes.h>
13 #include <asm/processor.h>
16 #include "ddrphy-init.h"
33 static u32 umc_cmdctla_plus[DRAM_FREQ_NR] = {0x45990b11, 0x36bb0f17};
34 static u32 umc_cmdctlb_plus[DRAM_FREQ_NR] = {0x16958924, 0x18c6aa24};
35 static u32 umc_spcctla[DRAM_FREQ_NR][DRAM_SZ_NR] = {
36 {0x00240512, 0x00350512},
37 {0x002b0617, 0x003f0617},
39 static u32 umc_spcctlb[DRAM_FREQ_NR] = {0x00ff0006, 0x00ff0008};
40 static u32 umc_rdatactl[DRAM_FREQ_NR] = {0x000a00ac, 0x000c00ae};
42 static int umc_get_rank(int ch)
44 return ch; /* ch0: rank0, ch1: rank1 for this SoC */
47 static void umc_start_ssif(void __iomem *ssif_base)
49 writel(0x00000000, ssif_base + 0x0000b004);
50 writel(0xffffffff, ssif_base + 0x0000c004);
51 writel(0x000fffcf, ssif_base + 0x0000c008);
52 writel(0x00000001, ssif_base + 0x0000b000);
53 writel(0x00000001, ssif_base + 0x0000c000);
54 writel(0x03010101, ssif_base + UMC_MDMCHSEL);
55 writel(0x03010100, ssif_base + UMC_DMDCHSEL);
57 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
58 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
59 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
60 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
61 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
62 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
63 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
64 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
65 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
66 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
68 writel(0x00000001, ssif_base + UMC_CPURST);
69 writel(0x00000001, ssif_base + UMC_IDSRST);
70 writel(0x00000001, ssif_base + UMC_IXMRST);
71 writel(0x00000001, ssif_base + UMC_MDMRST);
72 writel(0x00000001, ssif_base + UMC_MDDRST);
73 writel(0x00000001, ssif_base + UMC_SIORST);
74 writel(0x00000001, ssif_base + UMC_VIORST);
75 writel(0x00000001, ssif_base + UMC_FRCRST);
76 writel(0x00000001, ssif_base + UMC_RGLRST);
77 writel(0x00000001, ssif_base + UMC_AIORST);
78 writel(0x00000001, ssif_base + UMC_DMDRST);
81 static int umc_dramcont_init(void __iomem *dc_base, void __iomem *ca_base,
82 int freq, unsigned long size, bool ddr3plus)
84 enum dram_freq freq_e;
85 enum dram_size size_e;
88 pr_err("DDR3 standard is not supported\n");
94 freq_e = DRAM_FREQ_1333M;
97 freq_e = DRAM_FREQ_1600M;
100 pr_err("unsupported DRAM frequency %d MHz\n", freq);
108 size_e = DRAM_SZ_128M;
111 size_e = DRAM_SZ_256M;
114 pr_err("unsupported DRAM size 0x%08lx\n", size);
118 writel(umc_cmdctla_plus[freq_e], dc_base + UMC_CMDCTLA);
119 writel(umc_cmdctlb_plus[freq_e], dc_base + UMC_CMDCTLB);
120 writel(umc_spcctla[freq_e][size_e], dc_base + UMC_SPCCTLA);
121 writel(umc_spcctlb[freq_e], dc_base + UMC_SPCCTLB);
122 writel(umc_rdatactl[freq_e], dc_base + UMC_RDATACTL_D0);
123 writel(0x04060806, dc_base + UMC_WDATACTL_D0);
124 writel(0x04a02000, dc_base + UMC_DATASET);
125 writel(0x00000000, ca_base + 0x2300);
126 writel(0x00400020, dc_base + UMC_DCCGCTL);
127 writel(0x00000003, dc_base + 0x7000);
128 writel(0x0000000f, dc_base + 0x8000);
129 writel(0x000000c3, dc_base + 0x8004);
130 writel(0x00000071, dc_base + 0x8008);
131 writel(0x0000003b, dc_base + UMC_DICGCTLA);
132 writel(0x020a0808, dc_base + UMC_DICGCTLB);
133 writel(0x00000004, dc_base + UMC_FLOWCTLG);
134 writel(0x80000201, ca_base + 0xc20);
135 writel(0x0801e01e, dc_base + UMC_FLOWCTLA);
136 writel(0x00200000, dc_base + UMC_FLOWCTLB);
137 writel(0x00004444, dc_base + UMC_FLOWCTLC);
138 writel(0x200a0a00, dc_base + UMC_SPCSETB);
139 writel(0x00000000, dc_base + UMC_SPCSETD);
140 writel(0x00000520, dc_base + UMC_DFICUPDCTLA);
145 static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base,
146 int freq, unsigned long size, bool ddr3plus, int ch)
148 void __iomem *phy_base = dc_base + 0x00001000;
151 writel(UMC_INITSET_INIT1EN, dc_base + UMC_INITSET);
152 while (readl(dc_base + UMC_INITSTAT) & UMC_INITSTAT_INIT1ST)
155 writel(0x00000101, dc_base + UMC_DIOCTLA);
157 ret = uniphier_ld4_ddrphy_init(phy_base, freq, ddr3plus);
161 ddrphy_prepare_training(phy_base, umc_get_rank(ch));
162 ret = ddrphy_training(phy_base);
166 return umc_dramcont_init(dc_base, ca_base, freq, size, ddr3plus);
169 int uniphier_ld4_umc_init(const struct uniphier_board_data *bd)
171 void __iomem *umc_base = (void __iomem *)0x5b800000;
172 void __iomem *ca_base = umc_base + 0x00001000;
173 void __iomem *dc_base = umc_base + 0x00400000;
174 void __iomem *ssif_base = umc_base;
177 for (ch = 0; ch < DRAM_CH_NR; ch++) {
178 ret = umc_ch_init(dc_base, ca_base, bd->dram_freq,
179 bd->dram_ch[ch].size,
180 !!(bd->flags & UNIPHIER_BD_DDR3PLUS), ch);
182 pr_err("failed to initialize UMC ch%d\n", ch);
186 ca_base += 0x00001000;
187 dc_base += 0x00200000;
190 umc_start_ssif(ssif_base);