2 * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
4 * SPDX-License-Identifier: GPL-2.0+
11 #include "../sc-regs.h"
12 #include "../sg-regs.h"
14 static void dpll_init(void)
18 * Set DPLL SSC parameters for DPLLCTRL3
21 * [10] FREFSEL_TEST 0x1
26 tmp = readl(SC_DPLLCTRL3);
29 writel(tmp, SC_DPLLCTRL3);
32 * Set DPLL SSC parameters for DPLLCTRL
34 * [29:20] SSC_UPCNT 132 (0x084) 132 (0x084)
35 * [14:0] SSC_dK 6335(0x18bf) 12710(0x31a6)
37 tmp = readl(SC_DPLLCTRL);
39 #ifdef DPLL_SSC_RATE_1PER
44 writel(tmp, SC_DPLLCTRL);
47 * Set DPLL SSC parameters for DPLLCTRL2
50 * [26:20] SSC_M 79 (0x4f)
51 * [19:0] SSC_K 964689 (0xeb851)
53 tmp = readl(SC_DPLLCTRL2);
56 writel(tmp, SC_DPLLCTRL2);
59 static void upll_init(void)
61 u32 tmp, clk_mode_upll, clk_mode_axosel;
63 tmp = readl(SG_PINMON0);
64 clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
65 clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
67 /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
68 tmp = readl(SC_UPLLCTRL);
70 writel(tmp, SC_UPLLCTRL);
72 if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
73 if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
74 clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
79 /* AXO: default 24.576MHz */
85 writel(tmp, SC_UPLLCTRL);
87 /* set 1 to K_LD(UPLLCTRL.bit[27]) */
89 writel(tmp, SC_UPLLCTRL);
94 /* set 1 to SNRT(UPLLCTRL.bit[28]) */
96 writel(tmp, SC_UPLLCTRL);
99 static void vpll_init(void)
101 u32 tmp, clk_mode_axosel;
103 tmp = readl(SG_PINMON0);
104 clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
106 /* set 1 to VPLA27WP and VPLA27WP */
107 tmp = readl(SC_VPLL27ACTRL);
109 writel(tmp, SC_VPLL27ACTRL);
110 tmp = readl(SC_VPLL27BCTRL);
112 writel(tmp, SC_VPLL27BCTRL);
114 /* Set 0 to VPLA_K_LD and VPLB_K_LD */
115 tmp = readl(SC_VPLL27ACTRL3);
117 writel(tmp, SC_VPLL27ACTRL3);
118 tmp = readl(SC_VPLL27BCTRL3);
120 writel(tmp, SC_VPLL27BCTRL3);
122 /* Set 0 to VPLA_SNRST and VPLB_SNRST */
123 tmp = readl(SC_VPLL27ACTRL2);
125 writel(tmp, SC_VPLL27ACTRL2);
126 tmp = readl(SC_VPLL27BCTRL2);
128 writel(tmp, SC_VPLL27BCTRL2);
130 /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
131 tmp = readl(SC_VPLL27ACTRL2);
134 writel(tmp, SC_VPLL27ACTRL2);
135 tmp = readl(SC_VPLL27BCTRL2);
138 writel(tmp, SC_VPLL27BCTRL2);
140 if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
141 clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
143 tmp = readl(SC_VPLL27ACTRL3);
146 writel(tmp, SC_VPLL27ACTRL3);
147 tmp = readl(SC_VPLL27BCTRL3);
150 writel(tmp, SC_VPLL27BCTRL3);
152 /* AXO: default 24.576MHz */
153 tmp = readl(SC_VPLL27ACTRL3);
156 writel(tmp, SC_VPLL27ACTRL3);
157 tmp = readl(SC_VPLL27BCTRL3);
160 writel(tmp, SC_VPLL27BCTRL3);
163 /* Set 1 to VPLA_K_LD and VPLB_K_LD */
164 tmp = readl(SC_VPLL27ACTRL3);
166 writel(tmp, SC_VPLL27ACTRL3);
167 tmp = readl(SC_VPLL27BCTRL3);
169 writel(tmp, SC_VPLL27BCTRL3);
174 /* Set 0 to VPLA_SNRST and VPLB_SNRST */
175 tmp = readl(SC_VPLL27ACTRL2);
177 writel(tmp, SC_VPLL27ACTRL2);
178 tmp = readl(SC_VPLL27BCTRL2);
180 writel(tmp, SC_VPLL27BCTRL2);
182 /* set 0 to VPLA27WP and VPLA27WP */
183 tmp = readl(SC_VPLL27ACTRL);
185 writel(tmp, SC_VPLL27ACTRL);
186 tmp = readl(SC_VPLL27BCTRL);
188 writel(tmp, SC_VPLL27BCTRL);
191 int uniphier_sld8_pll_init(const struct uniphier_board_data *bd)
198 * Wait 500 usec until dpll get stable
199 * We wait 10 usec in upll_init() and vpll_init()
200 * so 20 usec can be saved here.