5 #ifndef __BFIN_PERIPHERAL_EMAC__
6 #define __BFIN_PERIPHERAL_EMAC__
8 /* EMAC_OPMODE Masks */
9 #define RE 0x00000001 /* Receiver Enable */
10 #define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
11 #define HU 0x00000010 /* Hash Filter Unicast Address */
12 #define HM 0x00000020 /* Hash Filter Multicast Address */
13 #define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
14 #define PR 0x00000080 /* Promiscuous Mode Enable */
15 #define IFE 0x00000100 /* Inverse Filtering Enable */
16 #define DBF 0x00000200 /* Disable Broadcast Frame Reception */
17 #define PBF 0x00000400 /* Pass Bad Frames Enable */
18 #define PSF 0x00000800 /* Pass Short Frames Enable */
19 #define RAF 0x00001000 /* Receive-All Mode */
20 #define TE 0x00010000 /* Transmitter Enable */
21 #define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
22 #define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
23 #define DC 0x00080000 /* Deferral Check */
24 #define BOLMT 0x00300000 /* Back-Off Limit */
25 #define BOLMT_10 0x00000000 /* 10-bit range */
26 #define BOLMT_8 0x00100000 /* 8-bit range */
27 #define BOLMT_4 0x00200000 /* 4-bit range */
28 #define BOLMT_1 0x00300000 /* 1-bit range */
29 #define DRTY 0x00400000 /* Disable TX Retry On Collision */
30 #define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
31 #define RMII 0x01000000 /* RMII/MII* Mode */
32 #define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
33 #define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
34 #define LB 0x08000000 /* Internal Loopback Enable */
35 #define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
37 /* EMAC_STAADD Masks */
38 #define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
39 #define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
40 #define STADISPRE 0x00000004 /* Disable Preamble Generation */
41 #define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
42 #define REGAD 0x000007C0 /* STA Register Address */
43 #define PHYAD 0x0000F800 /* PHY Device Address */
45 #define SET_REGAD(x) (((x) & 0x1F) << 6) /* Set STA Register Address */
46 #define SET_PHYAD(x) (((x) & 0x1F) << 11) /* Set PHY Device Address */
48 /* EMAC_STADAT Mask */
49 #define STADATA 0x0000FFFF /* Station Management Data */
52 #define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
53 #define FLCE 0x00000002 /* Flow Control Enable */
54 #define PCF 0x00000004 /* Pass Control Frames */
55 #define BKPRSEN 0x00000008 /* Enable Backpressure */
56 #define FLCPAUSE 0xFFFF0000 /* Pause Time */
58 #define SET_FLCPAUSE(x) (((x) & 0xFFFF) << 16) /* Set Pause Time */
60 /* EMAC_WKUP_CTL Masks */
61 #define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
62 #define MPKE 0x00000002 /* Magic Packet Enable */
63 #define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
64 #define GUWKE 0x00000008 /* Global Unicast Wake Enable */
65 #define MPKS 0x00000020 /* Magic Packet Received Status */
66 #define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
68 /* EMAC_WKUP_FFCMD Masks */
69 #define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
70 #define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
71 #define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
72 #define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
73 #define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
74 #define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
75 #define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
76 #define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
78 /* EMAC_WKUP_FFOFF Masks */
79 #define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
80 #define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
81 #define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
82 #define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
84 #define SET_WF0_OFF(x) (((x) & 0xFF) << 0) /* Set Wake-Up Filter 0 Byte Offset */
85 #define SET_WF1_OFF(x) (((x) & 0xFF) << 8) /* Set Wake-Up Filter 1 Byte Offset */
86 #define SET_WF2_OFF(x) (((x) & 0xFF) << 16) /* Set Wake-Up Filter 2 Byte Offset */
87 #define SET_WF3_OFF(x) (((x) & 0xFF) << 24) /* Set Wake-Up Filter 3 Byte Offset */
89 #define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
91 /* EMAC_WKUP_FFCRC0 Masks */
92 #define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
93 #define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
95 #define SET_WF0_CRC(x) (((x) & 0xFFFF) << 0) /* Set Wake-Up Filter 0 Target CRC */
96 #define SET_WF1_CRC(x) (((x) & 0xFFFF) << 16) /* Set Wake-Up Filter 1 Target CRC */
98 /* EMAC_WKUP_FFCRC1 Masks */
99 #define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
100 #define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
102 #define SET_WF2_CRC(x) (((x) & 0xFFFF) << 0) /* Set Wake-Up Filter 2 Target CRC */
103 #define SET_WF3_CRC(x) (((x) & 0xFFFF) << 16) /* Set Wake-Up Filter 3 Target CRC */
105 /* EMAC_SYSCTL Masks */
106 #define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
107 #define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
108 #define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
109 #define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
111 #define SET_MDCDIV(x) (((x) & 0x3F) << 8) /* Set MDC Clock Divisor */
113 /* EMAC_SYSTAT Masks */
114 #define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
115 #define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
116 #define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
117 #define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
118 #define WAKEDET 0x00000010 /* Wake-Up Detected Status */
119 #define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
120 #define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
121 #define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
123 /* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
124 #define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
125 #define RX_COMP 0x00001000 /* RX Frame Complete */
126 #define RX_OK 0x00002000 /* RX Frame Received With No Errors */
127 #define RX_LONG 0x00004000 /* RX Frame Too Long Error */
128 #define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
129 #define RX_CRC 0x00010000 /* RX Frame CRC Error */
130 #define RX_LEN 0x00020000 /* RX Frame Length Error */
131 #define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
132 #define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
133 #define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
134 #define RX_PHY 0x00200000 /* RX Frame PHY Error */
135 #define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
136 #define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
137 #define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
138 #define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
139 #define RX_CTL 0x04000000 /* RX Control Frame Indicator */
140 #define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
141 #define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
142 #define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
143 #define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
144 #define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
146 /* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
147 #define TX_COMP 0x00000001 /* TX Frame Complete */
148 #define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
149 #define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
150 #define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
151 #define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
152 #define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
153 #define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
154 #define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
155 #define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
156 #define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
157 #define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
158 #define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
159 #define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
160 #define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
161 #define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
163 /* EMAC_MMC_CTL Masks */
164 #define RSTC 0x00000001 /* Reset All Counters */
165 #define CROLL 0x00000002 /* Counter Roll-Over Enable */
166 #define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
167 #define MMCE 0x00000008 /* Enable MMC Counter Operation */
169 /* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
170 #define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
171 #define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
172 #define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
173 #define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
174 #define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
175 #define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
176 #define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
177 #define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
178 #define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
179 #define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
180 #define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
181 #define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
182 #define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
183 #define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
184 #define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
185 #define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
186 #define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
187 #define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
188 #define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
189 #define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
190 #define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
191 #define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
192 #define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
193 #define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
195 /* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
196 #define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
197 #define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
198 #define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
199 #define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
200 #define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
201 #define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
202 #define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
203 #define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
204 #define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
205 #define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
206 #define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
207 #define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
208 #define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
209 #define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
210 #define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
211 #define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
212 #define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
213 #define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
214 #define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
215 #define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
216 #define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
217 #define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
218 #define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
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