2 * timer.h -- ColdFire internal TIMER support defines.
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * SPDX-License-Identifier: GPL-2.0+
10 /****************************************************************************/
13 /****************************************************************************/
15 /****************************************************************************/
17 /****************************************************************************/
18 /* DMA Timer module registers */
19 typedef struct dtimer_ctrl {
20 #if defined(CONFIG_M5249) || defined(CONFIG_M5253) || defined(CONFIG_M5272)
21 u16 tmr; /* 0x00 Mode register */
23 u16 trr; /* 0x04 Reference register */
25 u16 tcr; /* 0x08 Capture register */
27 u16 tcn; /* 0x0C Counter register */
30 u8 ter; /* 0x11 Event register */
33 u16 tmr; /* 0x00 Mode register */
34 u8 txmr; /* 0x02 Extended Mode register */
35 u8 ter; /* 0x03 Event register */
36 u32 trr; /* 0x04 Reference register */
37 u32 tcr; /* 0x08 Capture register */
38 u32 tcn; /* 0x0C Counter register */
42 /*Programmable Interrupt Timer */
43 typedef struct pit_ctrl {
44 u16 pcsr; /* 0x00 Control and Status Register */
45 u16 pmr; /* 0x02 Modulus Register */
46 u16 pcntr; /* 0x04 Count Register */
49 /*********************************************************************
51 *********************************************************************/
52 /* Bit definitions and macros for DTMR */
53 #define DTIM_DTMR_RST (0x0001) /* Reset */
54 #define DTIM_DTMR_CLK(x) (((x)&0x0003)<<1) /* Input clock source */
55 #define DTIM_DTMR_FRR (0x0008) /* Free run/restart */
56 #define DTIM_DTMR_ORRI (0x0010) /* Output reference request/interrupt enable */
57 #define DTIM_DTMR_OM (0x0020) /* Output Mode */
58 #define DTIM_DTMR_CE(x) (((x)&0x0003)<<6) /* Capture Edge */
59 #define DTIM_DTMR_PS(x) (((x)&0x00FF)<<8) /* Prescaler value */
60 #define DTIM_DTMR_RST_EN (0x0001)
61 #define DTIM_DTMR_RST_RST (0x0000)
62 #define DTIM_DTMR_CE_ANY (0x00C0)
63 #define DTIM_DTMR_CE_FALL (0x0080)
64 #define DTIM_DTMR_CE_RISE (0x0040)
65 #define DTIM_DTMR_CE_NONE (0x0000)
66 #define DTIM_DTMR_CLK_DTIN (0x0006)
67 #define DTIM_DTMR_CLK_DIV16 (0x0004)
68 #define DTIM_DTMR_CLK_DIV1 (0x0002)
69 #define DTIM_DTMR_CLK_STOP (0x0000)
71 /* Bit definitions and macros for DTXMR */
72 #define DTIM_DTXMR_MODE16 (0x01) /* Increment Mode */
73 #define DTIM_DTXMR_DMAEN (0x80) /* DMA request */
75 /* Bit definitions and macros for DTER */
76 #define DTIM_DTER_CAP (0x01) /* Capture event */
77 #define DTIM_DTER_REF (0x02) /* Output reference event */
79 /*********************************************************************
81 * Programmable Interrupt Timer Modules (PIT)
83 *********************************************************************/
85 /* Bit definitions and macros for PCSR */
86 #define PIT_PCSR_EN (0x0001)
87 #define PIT_PCSR_RLD (0x0002)
88 #define PIT_PCSR_PIF (0x0004)
89 #define PIT_PCSR_PIE (0x0008)
90 #define PIT_PCSR_OVW (0x0010)
91 #define PIT_PCSR_HALTED (0x0020)
92 #define PIT_PCSR_DOZE (0x0040)
93 #define PIT_PCSR_PRE(x) (((x)&0x000F)<<8)
95 /* Bit definitions and macros for PMR */
96 #define PIT_PMR_PM(x) (x)
98 /* Bit definitions and macros for PCNTR */
99 #define PIT_PCNTR_PC(x) (x)
101 /****************************************************************************/