2 * Cache-handling routined for MIPS CPUs
4 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm-offsets.h>
28 #include <asm/regdef.h>
29 #include <asm/mipsregs.h>
30 #include <asm/addrspace.h>
31 #include <asm/cacheops.h>
36 * 16kB is the maximum size of instruction and data caches on MIPS 4K,
37 * 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience.
39 * Note that the above size is the maximum size of primary cache. U-Boot
40 * doesn't have L2 cache support for now.
42 #define MIPS_MAX_CACHE_SIZE 0x10000
44 #define INDEX_BASE CKSEG0
46 .macro cache_op op addr
54 .macro f_fill64 dst, offset, val
55 LONG_S \val, (\offset + 0 * LONGSIZE)(\dst)
56 LONG_S \val, (\offset + 1 * LONGSIZE)(\dst)
57 LONG_S \val, (\offset + 2 * LONGSIZE)(\dst)
58 LONG_S \val, (\offset + 3 * LONGSIZE)(\dst)
59 LONG_S \val, (\offset + 4 * LONGSIZE)(\dst)
60 LONG_S \val, (\offset + 5 * LONGSIZE)(\dst)
61 LONG_S \val, (\offset + 6 * LONGSIZE)(\dst)
62 LONG_S \val, (\offset + 7 * LONGSIZE)(\dst)
64 LONG_S \val, (\offset + 8 * LONGSIZE)(\dst)
65 LONG_S \val, (\offset + 9 * LONGSIZE)(\dst)
66 LONG_S \val, (\offset + 10 * LONGSIZE)(\dst)
67 LONG_S \val, (\offset + 11 * LONGSIZE)(\dst)
68 LONG_S \val, (\offset + 12 * LONGSIZE)(\dst)
69 LONG_S \val, (\offset + 13 * LONGSIZE)(\dst)
70 LONG_S \val, (\offset + 14 * LONGSIZE)(\dst)
71 LONG_S \val, (\offset + 15 * LONGSIZE)(\dst)
76 * mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz)
78 LEAF(mips_init_icache)
81 /* clear tag to invalidate */
84 1: cache_op INDEX_STORE_TAG_I t0
87 /* fill once, so data field parity is correct */
92 /* invalidate again - prudent but not strictly neccessary */
94 1: cache_op INDEX_STORE_TAG_I t0
101 * mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz)
103 LEAF(mips_init_dcache)
107 PTR_LI t0, INDEX_BASE
109 1: cache_op INDEX_STORE_TAG_D t0
112 /* load from each line (in cached space) */
113 PTR_LI t0, INDEX_BASE
114 2: LONG_L zero, 0(t0)
118 PTR_LI t0, INDEX_BASE
119 1: cache_op INDEX_STORE_TAG_D t0
123 END(mips_init_dcache)
126 * mips_cache_reset - low level initialisation of the primary caches
128 * This routine initialises the primary caches to ensure that they have good
129 * parity. It must be called by the ROM before any cached locations are used
130 * to prevent the possibility of data with bad parity being written to memory.
132 * To initialise the instruction cache it is essential that a source of data
133 * with good parity is available. This routine will initialise an area of
134 * memory starting at location zero to be used as a source of parity.
139 NESTED(mips_cache_reset, 0, ra)
141 li t2, CONFIG_SYS_ICACHE_SIZE
142 li t3, CONFIG_SYS_DCACHE_SIZE
143 li t8, CONFIG_SYS_CACHELINE_SIZE
145 li v0, MIPS_MAX_CACHE_SIZE
148 * Now clear that much memory starting from zero.
153 f_fill64 a0, -64, zero
157 * The caches are probably in an indeterminate state,
158 * so we force good parity into them by doing an
159 * invalidate, load/fill, invalidate for each line.
163 * Assume bottom of RAM will generate good parity for the cache.
167 * Initialize the I-cache first,
171 PTR_LA v1, mips_init_icache
175 * then initialize D-cache.
179 PTR_LA v1, mips_init_dcache
183 END(mips_cache_reset)
186 * dcache_status - get cache status
188 * RETURNS: 0 - cache disabled; 1 - cache enabled
193 li t1, CONF_CM_UNCACHED
194 andi t0, t0, CONF_CM_CMASK
202 * dcache_disable - disable cache
211 ori t0, t0, CONF_CM_UNCACHED
217 * dcache_enable - enable cache
224 ori t0, CONF_CM_CMASK
225 xori t0, CONF_CM_CMASK
226 ori t0, CONF_CM_CACHABLE_NONCOHERENT