2 * Cache-handling routined for MIPS CPUs
4 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
6 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm-offsets.h>
12 #include <asm/regdef.h>
13 #include <asm/mipsregs.h>
14 #include <asm/addrspace.h>
15 #include <asm/cacheops.h>
20 * 16kB is the maximum size of instruction and data caches on MIPS 4K,
21 * 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience.
23 * Note that the above size is the maximum size of primary cache. U-Boot
24 * doesn't have L2 cache support for now.
26 #define MIPS_MAX_CACHE_SIZE 0x10000
28 #define INDEX_BASE CKSEG0
30 .macro cache_op op addr
38 .macro f_fill64 dst, offset, val
39 LONG_S \val, (\offset + 0 * LONGSIZE)(\dst)
40 LONG_S \val, (\offset + 1 * LONGSIZE)(\dst)
41 LONG_S \val, (\offset + 2 * LONGSIZE)(\dst)
42 LONG_S \val, (\offset + 3 * LONGSIZE)(\dst)
43 LONG_S \val, (\offset + 4 * LONGSIZE)(\dst)
44 LONG_S \val, (\offset + 5 * LONGSIZE)(\dst)
45 LONG_S \val, (\offset + 6 * LONGSIZE)(\dst)
46 LONG_S \val, (\offset + 7 * LONGSIZE)(\dst)
48 LONG_S \val, (\offset + 8 * LONGSIZE)(\dst)
49 LONG_S \val, (\offset + 9 * LONGSIZE)(\dst)
50 LONG_S \val, (\offset + 10 * LONGSIZE)(\dst)
51 LONG_S \val, (\offset + 11 * LONGSIZE)(\dst)
52 LONG_S \val, (\offset + 12 * LONGSIZE)(\dst)
53 LONG_S \val, (\offset + 13 * LONGSIZE)(\dst)
54 LONG_S \val, (\offset + 14 * LONGSIZE)(\dst)
55 LONG_S \val, (\offset + 15 * LONGSIZE)(\dst)
60 * mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz)
62 LEAF(mips_init_icache)
65 /* clear tag to invalidate */
68 1: cache_op INDEX_STORE_TAG_I t0
71 /* fill once, so data field parity is correct */
76 /* invalidate again - prudent but not strictly neccessary */
78 1: cache_op INDEX_STORE_TAG_I t0
85 * mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz)
87 LEAF(mips_init_dcache)
93 1: cache_op INDEX_STORE_TAG_D t0
96 /* load from each line (in cached space) */
102 PTR_LI t0, INDEX_BASE
103 1: cache_op INDEX_STORE_TAG_D t0
107 END(mips_init_dcache)
110 * mips_cache_reset - low level initialisation of the primary caches
112 * This routine initialises the primary caches to ensure that they have good
113 * parity. It must be called by the ROM before any cached locations are used
114 * to prevent the possibility of data with bad parity being written to memory.
116 * To initialise the instruction cache it is essential that a source of data
117 * with good parity is available. This routine will initialise an area of
118 * memory starting at location zero to be used as a source of parity.
123 NESTED(mips_cache_reset, 0, ra)
125 li t2, CONFIG_SYS_ICACHE_SIZE
126 li t3, CONFIG_SYS_DCACHE_SIZE
127 li t8, CONFIG_SYS_CACHELINE_SIZE
129 li v0, MIPS_MAX_CACHE_SIZE
132 * Now clear that much memory starting from zero.
137 f_fill64 a0, -64, zero
141 * The caches are probably in an indeterminate state,
142 * so we force good parity into them by doing an
143 * invalidate, load/fill, invalidate for each line.
147 * Assume bottom of RAM will generate good parity for the cache.
151 * Initialize the I-cache first,
155 PTR_LA v1, mips_init_icache
159 * then initialize D-cache.
163 PTR_LA v1, mips_init_dcache
167 END(mips_cache_reset)
170 * dcache_status - get cache status
172 * RETURNS: 0 - cache disabled; 1 - cache enabled
177 li t1, CONF_CM_UNCACHED
178 andi t0, t0, CONF_CM_CMASK
186 * dcache_disable - disable cache
195 ori t0, t0, CONF_CM_UNCACHED
201 * dcache_enable - enable cache
208 ori t0, CONF_CM_CMASK
209 xori t0, CONF_CM_CMASK
210 ori t0, CONF_CM_CACHABLE_NONCOHERENT