2 * Startup Code for MIPS64 CPU-core
4 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any dlater version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICUdlaR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Pdlace, Suite 330, Boston,
25 #include <asm-offsets.h>
27 #include <asm/regdef.h>
28 #include <asm/mipsregs.h>
30 #ifndef CONFIG_SYS_MIPS_CACHE_MODE
31 #define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
35 * For the moment disable interrupts, mark the kernel mode and
36 * set ST0_KX so that the CPU does not spit fire when using
39 .macro setup_c0_status set clr
42 or t0, ST0_CU0 | \set | 0x1f | \clr
55 /* U-boot entry point */
60 /* TLB refill, 32 bit task */
65 /* XTLB refill, 64 bit task */
70 /* Cache error exception */
75 /* General exception */
80 /* Catch interrupt exceptions */
85 /* EJTAG debug exception */
92 /* Clear watch registers */
93 dmtc0 zero, CP0_WATCHLO
94 dmtc0 zero, CP0_WATCHHI
96 /* WP(Watch Pending), SW0/1 should be cleared */
99 setup_c0_status ST0_KX 0
103 mtc0 zero, CP0_COMPARE
105 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
106 /* CONFIG0 register */
107 dli t0, CONF_CM_UNCACHED
112 * Initialize $gp, force 8 byte alignment of bal instruction to forbid
113 * the compiler to put nop's between bal and _gp. This is required to
114 * keep _gp and ra aligned to 8 byte.
123 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
124 /* Initialize any external memory */
125 dla t9, lowlevel_init
129 /* Initialize caches... */
130 dla t9, mips_cache_reset
134 /* ... and enable them */
135 dli t0, CONFIG_SYS_MIPS_CACHE_MODE
139 /* Set up temporary stack */
140 dli sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
147 * void relocate_code (addr_sp, gd, addr_moni)
149 * This "function" does not return, instead it continues in RAM
150 * after relocating the monitor code.
154 * a2 = destination address
159 move sp, a0 # set new stack pointer
161 move s0, a1 # save gd in s0
162 move s2, a2 # save destination address in s2
164 dli t0, CONFIG_SYS_MONITOR_BASE
165 dsub s1, s2, t0 # s1 <-- relocation offset
168 ld t2, -24(t3) # t2 <-- uboot_end_data
171 dadd gp, s1 # adjust gp
174 * t0 = source address
175 * t1 = target address
176 * t2 = source end address
185 /* If caches were enabled, we would have to flush them here. */
186 dsub a1, t1, s2 # a1 <-- size
189 move a0, s2 # a0 <-- destination address
191 /* Jump to where we've relocated ourselves */
192 daddi t0, s2, in_ram - _start
196 .dword _GLOBAL_OFFSET_TABLE_
197 .dword uboot_end_data
199 .dword num_got_entries
203 * Now we want to update GOT.
205 * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
206 * generated by GNU ld. Skip these reserved entries from relocation.
208 ld t3, -8(t0) # t3 <-- num_got_entries
209 ld t8, -32(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_
210 dadd t8, s1 # t8 now holds relocated _G_O_T_
211 daddi t8, t8, 16 # skipping first two entries
224 ld t1, -24(t0) # t1 <-- uboot_end_data
225 ld t2, -16(t0) # t2 <-- uboot_end
226 dadd t1, s1 # adjust pointers
235 move a0, s0 # a0 <-- gd