2 * Startup Code for MIPS32 CPU-core
4 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
6 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm-offsets.h>
12 #include <asm/regdef.h>
13 #include <asm/mipsregs.h>
15 #ifndef CONFIG_SYS_INIT_SP_ADDR
16 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
17 CONFIG_SYS_INIT_SP_OFFSET)
26 # ifdef CONFIG_SYS_LITTLE_ENDIAN
27 # define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
28 (((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym))
30 # define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
31 ((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24)
33 # define MIPS_RELOC MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03)
34 # define STATUS_SET ST0_KX
38 * For the moment disable interrupts, mark the kernel mode and
39 * set ST0_KX so that the CPU does not spit fire when using
42 .macro setup_c0_status set clr
45 or t0, ST0_CU0 | \set | 0x1f | \clr
56 /* U-Boot entry point */
61 #if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG)
63 * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
64 * access external NOR flashes. If the board boots from NOR flash the
65 * internal BootROM does a blind read at address 0xB0000010 to read the
66 * initial configuration for that EBU in order to access the flash
67 * device with correct parameters. This config option is board-specific.
69 .word CONFIG_SYS_XWAY_EBU_BOOTCFG
71 #elif defined(CONFIG_MALTA)
73 * Linux expects the Board ID here.
75 .word 0x00000420 # 0x420 (Malta Board with CoreLV)
80 /* TLB refill, 32 bit task */
85 /* XTLB refill, 64 bit task */
90 /* Cache error exception */
95 /* General exception */
100 /* Catch interrupt exceptions */
105 /* EJTAG debug exception */
111 #if __mips_isa_rev >= 6
112 mfc0 t0, CP0_CONFIG, 5
113 and t0, t0, MIPS_CONF5_VP
118 mfc0 t0, CP0_GLOBALNUMBER
121 1: mfc0 t0, CP0_EBASE
122 and t0, t0, EBASE_CPUNUM
124 /* Hang if this isn't the first CPU in the system */
131 /* Clear watch registers */
132 4: MTC0 zero, CP0_WATCHLO
133 mtc0 zero, CP0_WATCHHI
135 /* WP(Watch Pending), SW0/1 should be cleared */
138 setup_c0_status STATUS_SET 0
142 mtc0 zero, CP0_COMPARE
144 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
146 and t0, t0, MIPS_CONF_IMPL
147 or t0, t0, CONF_CM_UNCACHED
153 * Initialize $gp, force pointer sized alignment of bal instruction to
154 * forbid the compiler to put nop's between bal and _gp. This is
155 * required to keep _gp and ra aligned to 8 byte.
164 #ifdef CONFIG_MIPS_CM
165 PTR_LA t9, mips_cm_map
170 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
171 # ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
172 /* Initialize any external memory */
173 PTR_LA t9, lowlevel_init
178 /* Initialize caches... */
179 PTR_LA t9, mips_cache_reset
183 # ifndef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
184 /* Initialize any external memory */
185 PTR_LA t9, lowlevel_init
191 /* Set up temporary stack */
193 PTR_LI t1, CONFIG_SYS_INIT_SP_ADDR
194 and sp, t1, t0 # force 16 byte alignment
196 sp, sp, GD_SIZE # reserve space for gd
197 and sp, sp, t0 # force 16 byte alignment
198 move k0, sp # save gd pointer
199 #ifdef CONFIG_SYS_MALLOC_F_LEN
200 li t2, CONFIG_SYS_MALLOC_F_LEN
202 sp, sp, t2 # reserve space for early malloc
203 and sp, sp, t0 # force 16 byte alignment
212 PTR_ADDIU t0, PTRSIZE
214 #ifdef CONFIG_SYS_MALLOC_F_LEN
215 PTR_S sp, GD_MALLOC_BASE(k0) # gd->malloc_base offset
218 move a0, zero # a0 <-- boot_flags = 0
219 PTR_LA t9, board_init_f
226 * void relocate_code (addr_sp, gd, addr_moni)
228 * This "function" does not return, instead it continues in RAM
229 * after relocating the monitor code.
233 * a2 = destination address
236 move sp, a0 # set new stack pointer
239 move s0, a1 # save gd in s0
240 move s2, a2 # save destination address in s2
242 PTR_LI t0, CONFIG_SYS_MONITOR_BASE
243 PTR_SUB s1, s2, t0 # s1 <-- relocation offset
245 PTR_LA t2, __image_copy_end
249 * t0 = source address
250 * t1 = target address
251 * t2 = source end address
261 * Now we want to update GOT.
263 * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
264 * generated by GNU ld. Skip these reserved entries from relocation.
266 PTR_LA t3, num_got_entries
267 PTR_LA t8, _GLOBAL_OFFSET_TABLE_
268 PTR_ADD t8, s1 # t8 now holds relocated _G_O_T_
269 PTR_ADDIU t8, t8, 2 * PTRSIZE # skipping first two entries
279 PTR_ADDIU t8, PTRSIZE
281 /* Update dynamic relocations */
282 PTR_LA t1, __rel_dyn_start
283 PTR_LA t2, __rel_dyn_end
285 b 2f # skip first reserved entry
286 PTR_ADDIU t1, 2 * PTRSIZE
289 lw t8, -4(t1) # t8 <-- relocation info
291 PTR_LI t3, MIPS_RELOC
292 bne t8, t3, 2f # skip non-MIPS_RELOC entries
295 PTR_L t3, -(2 * PTRSIZE)(t1) # t3 <-- location to fix up in FLASH
297 PTR_L t8, 0(t3) # t8 <-- original pointer
298 PTR_ADD t8, s1 # t8 <-- adjusted pointer
300 PTR_ADD t3, s1 # t3 <-- location to fix up in RAM
305 PTR_ADDIU t1, 2 * PTRSIZE # each rel.dyn entry is 2*PTRSIZE bytes
308 * Flush caches to ensure our newly modified instructions are visible
309 * to the instruction cache. We're still running with the old GOT, so
310 * apply the reloc offset to the start address.
312 PTR_LA a0, __text_start
313 PTR_LA a1, __text_end
315 PTR_LA t9, flush_cache
319 PTR_ADD gp, s1 # adjust gp
324 * GOT is now relocated. Thus __bss_start and __bss_end can be
325 * accessed directly via $gp.
327 PTR_LA t1, __bss_start # t1 <-- __bss_start
328 PTR_LA t2, __bss_end # t2 <-- __bss_end
333 PTR_ADDIU t1, PTRSIZE
335 move a0, s0 # a0 <-- gd
337 PTR_LA t9, board_init_r