2 * Startup Code for MIPS32 CPU-core
4 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
6 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm-offsets.h>
12 #include <asm/regdef.h>
13 #include <asm/mipsregs.h>
15 #ifndef CONFIG_SYS_INIT_SP_ADDR
16 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
17 CONFIG_SYS_INIT_SP_OFFSET)
26 # ifdef CONFIG_SYS_LITTLE_ENDIAN
27 # define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
28 (((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym))
30 # define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
31 ((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24)
33 # define MIPS_RELOC MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03)
34 # define STATUS_SET ST0_KX
40 MTC0 zero, CP0_WATCHLO,\sel
41 mtc0 t1, CP0_WATCHHI,\sel
42 mfc0 t0, CP0_WATCHHI,\sel
47 .macro uhi_mips_exception
48 move k0, t9 # preserve t9 in k0
49 move k1, a0 # preserve a0 in k1
50 li t9, 15 # UHI exception operation
51 li a0, 0 # Use hard register context
52 sdbbp 1 # Invoke UHI operation
57 PTR_LI t1, CONFIG_SYS_INIT_SP_ADDR
58 and sp, t1, t0 # force 16 byte alignment
60 sp, sp, GD_SIZE # reserve space for gd
61 and sp, sp, t0 # force 16 byte alignment
62 move k0, sp # save gd pointer
63 #if CONFIG_VAL(SYS_MALLOC_F_LEN)
64 li t2, CONFIG_VAL(SYS_MALLOC_F_LEN)
66 sp, sp, t2 # reserve space for early malloc
67 and sp, sp, t0 # force 16 byte alignment
78 #if CONFIG_VAL(SYS_MALLOC_F_LEN)
79 PTR_S sp, GD_MALLOC_BASE(k0) # gd->malloc_base offset
84 /* U-Boot entry point */
86 mtc0 zero, CP0_COUNT # clear cp0 count for most accurate boot timing
88 #if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG)
90 * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
91 * access external NOR flashes. If the board boots from NOR flash the
92 * internal BootROM does a blind read at address 0xB0000010 to read the
93 * initial configuration for that EBU in order to access the flash
94 * device with correct parameters. This config option is board-specific.
97 .word CONFIG_SYS_XWAY_EBU_BOOTCFG
100 #if defined(CONFIG_MALTA)
102 * Linux expects the Board ID here.
105 .word 0x00000420 # 0x420 (Malta Board with CoreLV)
109 #if defined(CONFIG_ROM_EXCEPTION_VECTORS)
111 * Exception vector entry points. When running from ROM, an exception
112 * cannot be handled. Halt execution and transfer control to debugger,
113 * if one is attached.
116 /* TLB refill, 32 bit task */
120 /* XTLB refill, 64 bit task */
124 /* Cache error exception */
128 /* General exception */
132 /* Catch interrupt exceptions */
136 /* EJTAG debug exception */
144 #if __mips_isa_rev >= 6
145 mfc0 t0, CP0_CONFIG, 5
146 and t0, t0, MIPS_CONF5_VP
151 mfc0 t0, CP0_GLOBALNUMBER
154 #ifdef CONFIG_ARCH_BMIPS
155 1: mfc0 t0, CP0_DIAGNOSTIC, 3
156 and t0, t0, (1 << 31)
158 1: mfc0 t0, CP0_EBASE
159 and t0, t0, EBASE_CPUNUM
162 /* Hang if this isn't the first CPU in the system */
169 /* Init CP0 Status */
170 4: mfc0 t0, CP0_STATUS
172 or t0, ST0_BEV | ST0_ERL | STATUS_SET
176 * Check whether CP0 Config1 is implemented. If not continue
177 * with legacy Watch register initialization.
184 * Check WR bit in CP0 Config1 to determine if Watch registers
187 mfc0 t0, CP0_CONFIG, 1
192 /* Clear Watch Status bits and disable watch exceptions */
193 li t1, 0x7 # Clear I, R and W conditions
206 MTC0 zero, CP0_WATCHLO
207 mtc0 zero, CP0_WATCHHI
210 /* Clear WP, IV and SW interrupts */
213 /* Clear timer interrupt (CP0_COUNT cleared on branch to 'reset') */
214 mtc0 zero, CP0_COMPARE
216 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
218 and t0, t0, MIPS_CONF_IMPL
219 or t0, t0, CONF_CM_UNCACHED
224 #ifdef CONFIG_MIPS_CM
225 PTR_LA t9, mips_cm_map
230 #ifdef CONFIG_MIPS_INIT_STACK_IN_SRAM
231 /* Set up initial stack and global data */
234 # ifdef CONFIG_DEBUG_UART
235 /* Earliest point to set up debug uart */
236 PTR_LA t9, debug_uart_init
242 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
243 # ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
244 /* Initialize any external memory */
245 PTR_LA t9, lowlevel_init
250 /* Initialize caches... */
251 PTR_LA t9, mips_cache_reset
255 # ifndef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
256 /* Initialize any external memory */
257 PTR_LA t9, lowlevel_init
263 #ifndef CONFIG_MIPS_INIT_STACK_IN_SRAM
264 /* Set up initial stack and global data */
267 # ifdef CONFIG_DEBUG_UART
268 /* Earliest point to set up debug uart */
269 PTR_LA t9, debug_uart_init
275 move a0, zero # a0 <-- boot_flags = 0
276 PTR_LA t9, board_init_f