2 * Startup Code for MIPS32 CPU-core
4 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
6 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm-offsets.h>
12 #include <asm/regdef.h>
13 #include <asm/mipsregs.h>
15 #ifndef CONFIG_SYS_INIT_SP_ADDR
16 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
17 CONFIG_SYS_INIT_SP_OFFSET)
26 # ifdef CONFIG_SYS_LITTLE_ENDIAN
27 # define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
28 (((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym))
30 # define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
31 ((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24)
33 # define MIPS_RELOC MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03)
34 # define STATUS_SET ST0_KX
40 MTC0 zero, CP0_WATCHLO,\sel
41 mtc0 t1, CP0_WATCHHI,\sel
42 mfc0 t0, CP0_WATCHHI,\sel
47 .macro uhi_mips_exception
48 move k0, t9 # preserve t9 in k0
49 move k1, a0 # preserve a0 in k1
50 li t9, 15 # UHI exception operation
51 li a0, 0 # Use hard register context
52 sdbbp 1 # Invoke UHI operation
57 PTR_LI t1, CONFIG_SYS_INIT_SP_ADDR
58 and sp, t1, t0 # force 16 byte alignment
60 sp, sp, GD_SIZE # reserve space for gd
61 and sp, sp, t0 # force 16 byte alignment
62 move k0, sp # save gd pointer
63 #ifdef CONFIG_SYS_MALLOC_F_LEN
64 li t2, CONFIG_SYS_MALLOC_F_LEN
66 sp, sp, t2 # reserve space for early malloc
67 and sp, sp, t0 # force 16 byte alignment
78 #ifdef CONFIG_SYS_MALLOC_F_LEN
79 PTR_S sp, GD_MALLOC_BASE(k0) # gd->malloc_base offset
84 /* U-Boot entry point */
86 mtc0 zero, CP0_COUNT # clear cp0 count for most accurate boot timing
88 #if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG)
90 * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
91 * access external NOR flashes. If the board boots from NOR flash the
92 * internal BootROM does a blind read at address 0xB0000010 to read the
93 * initial configuration for that EBU in order to access the flash
94 * device with correct parameters. This config option is board-specific.
97 .word CONFIG_SYS_XWAY_EBU_BOOTCFG
100 #if defined(CONFIG_MALTA)
102 * Linux expects the Board ID here.
105 .word 0x00000420 # 0x420 (Malta Board with CoreLV)
109 #if defined(CONFIG_ROM_EXCEPTION_VECTORS)
111 * Exception vector entry points. When running from ROM, an exception
112 * cannot be handled. Halt execution and transfer control to debugger,
113 * if one is attached.
116 /* TLB refill, 32 bit task */
120 /* XTLB refill, 64 bit task */
124 /* Cache error exception */
128 /* General exception */
132 /* Catch interrupt exceptions */
136 /* EJTAG debug exception */
144 #if __mips_isa_rev >= 6
145 mfc0 t0, CP0_CONFIG, 5
146 and t0, t0, MIPS_CONF5_VP
151 mfc0 t0, CP0_GLOBALNUMBER
154 1: mfc0 t0, CP0_EBASE
155 and t0, t0, EBASE_CPUNUM
157 /* Hang if this isn't the first CPU in the system */
164 /* Init CP0 Status */
165 4: mfc0 t0, CP0_STATUS
167 or t0, ST0_BEV | ST0_ERL | STATUS_SET
171 * Check whether CP0 Config1 is implemented. If not continue
172 * with legacy Watch register initialization.
179 * Check WR bit in CP0 Config1 to determine if Watch registers
182 mfc0 t0, CP0_CONFIG, 1
187 /* Clear Watch Status bits and disable watch exceptions */
188 li t1, 0x7 # Clear I, R and W conditions
201 MTC0 zero, CP0_WATCHLO
202 mtc0 zero, CP0_WATCHHI
205 /* Clear WP, IV and SW interrupts */
208 /* Clear timer interrupt (CP0_COUNT cleared on branch to 'reset') */
209 mtc0 zero, CP0_COMPARE
211 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
213 and t0, t0, MIPS_CONF_IMPL
214 or t0, t0, CONF_CM_UNCACHED
220 * Initialize $gp, force pointer sized alignment of bal instruction to
221 * forbid the compiler to put nop's between bal and _gp. This is
222 * required to keep _gp and ra aligned to 8 byte.
231 #ifdef CONFIG_MIPS_CM
232 PTR_LA t9, mips_cm_map
237 #ifdef CONFIG_MIPS_INIT_STACK_IN_SRAM
238 /* Set up initial stack and global data */
241 # ifdef CONFIG_DEBUG_UART
242 /* Earliest point to set up debug uart */
243 PTR_LA t9, debug_uart_init
249 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
250 # ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
251 /* Initialize any external memory */
252 PTR_LA t9, lowlevel_init
257 /* Initialize caches... */
258 PTR_LA t9, mips_cache_reset
262 # ifndef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
263 /* Initialize any external memory */
264 PTR_LA t9, lowlevel_init
270 #ifndef CONFIG_MIPS_INIT_STACK_IN_SRAM
271 /* Set up initial stack and global data */
274 # ifdef CONFIG_DEBUG_UART
275 /* Earliest point to set up debug uart */
276 PTR_LA t9, debug_uart_init
282 move a0, zero # a0 <-- boot_flags = 0
283 PTR_LA t9, board_init_f
291 * void relocate_code (addr_sp, gd, addr_moni)
293 * This "function" does not return, instead it continues in RAM
294 * after relocating the monitor code.
298 * a2 = destination address
301 move sp, a0 # set new stack pointer
304 move s0, a1 # save gd in s0
305 move s2, a2 # save destination address in s2
307 PTR_LI t0, CONFIG_SYS_MONITOR_BASE
308 PTR_SUB s1, s2, t0 # s1 <-- relocation offset
310 PTR_LA t2, __image_copy_end
314 * t0 = source address
315 * t1 = target address
316 * t2 = source end address
326 * Now we want to update GOT.
328 * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
329 * generated by GNU ld. Skip these reserved entries from relocation.
331 PTR_LA t3, num_got_entries
332 PTR_LA t8, _GLOBAL_OFFSET_TABLE_
333 PTR_ADD t8, s1 # t8 now holds relocated _G_O_T_
334 PTR_ADDIU t8, t8, 2 * PTRSIZE # skipping first two entries
344 PTR_ADDIU t8, PTRSIZE
346 /* Update dynamic relocations */
347 PTR_LA t1, __rel_dyn_start
348 PTR_LA t2, __rel_dyn_end
350 b 2f # skip first reserved entry
351 PTR_ADDIU t1, 2 * PTRSIZE
354 lw t8, -4(t1) # t8 <-- relocation info
356 PTR_LI t3, MIPS_RELOC
357 bne t8, t3, 2f # skip non-MIPS_RELOC entries
360 PTR_L t3, -(2 * PTRSIZE)(t1) # t3 <-- location to fix up in FLASH
362 PTR_L t8, 0(t3) # t8 <-- original pointer
363 PTR_ADD t8, s1 # t8 <-- adjusted pointer
365 PTR_ADD t3, s1 # t3 <-- location to fix up in RAM
370 PTR_ADDIU t1, 2 * PTRSIZE # each rel.dyn entry is 2*PTRSIZE bytes
373 * Flush caches to ensure our newly modified instructions are visible
374 * to the instruction cache. We're still running with the old GOT, so
375 * apply the reloc offset to the start address.
377 PTR_LA a0, __text_start
378 PTR_LA a1, __text_end
380 PTR_LA t9, flush_cache
384 PTR_ADD gp, s1 # adjust gp
389 * GOT is now relocated. Thus __bss_start and __bss_end can be
390 * accessed directly via $gp.
392 PTR_LA t1, __bss_start # t1 <-- __bss_start
393 PTR_LA t2, __bss_end # t2 <-- __bss_end
398 PTR_ADDIU t1, PTRSIZE
400 move a0, s0 # a0 <-- gd
402 PTR_LA t9, board_init_r