2 * Startup Code for MIPS32 CPU-core
4 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
6 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm-offsets.h>
12 #include <asm/regdef.h>
13 #include <asm/mipsregs.h>
15 #ifndef CONFIG_SYS_MIPS_CACHE_MODE
16 #define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
19 #ifndef CONFIG_SYS_INIT_SP_ADDR
20 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
21 CONFIG_SYS_INIT_SP_OFFSET)
30 # ifdef CONFIG_SYS_LITTLE_ENDIAN
31 # define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
32 (((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym))
34 # define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
35 ((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24)
37 # define MIPS_RELOC MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03)
38 # define STATUS_SET ST0_KX
42 * For the moment disable interrupts, mark the kernel mode and
43 * set ST0_KX so that the CPU does not spit fire when using
46 .macro setup_c0_status set clr
49 or t0, ST0_CU0 | \set | 0x1f | \clr
60 /* U-Boot entry point */
65 #if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG)
67 * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
68 * access external NOR flashes. If the board boots from NOR flash the
69 * internal BootROM does a blind read at address 0xB0000010 to read the
70 * initial configuration for that EBU in order to access the flash
71 * device with correct parameters. This config option is board-specific.
73 .word CONFIG_SYS_XWAY_EBU_BOOTCFG
75 #elif defined(CONFIG_MALTA)
77 * Linux expects the Board ID here.
79 .word 0x00000420 # 0x420 (Malta Board with CoreLV)
84 /* TLB refill, 32 bit task */
89 /* XTLB refill, 64 bit task */
94 /* Cache error exception */
99 /* General exception */
104 /* Catch interrupt exceptions */
109 /* EJTAG debug exception */
116 /* Clear watch registers */
117 MTC0 zero, CP0_WATCHLO
118 mtc0 zero, CP0_WATCHHI
120 /* WP(Watch Pending), SW0/1 should be cleared */
123 setup_c0_status STATUS_SET 0
127 mtc0 zero, CP0_COMPARE
129 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
130 /* CONFIG0 register */
131 li t0, CONF_CM_UNCACHED
136 * Initialize $gp, force pointer sized alignment of bal instruction to
137 * forbid the compiler to put nop's between bal and _gp. This is
138 * required to keep _gp and ra aligned to 8 byte.
147 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
148 /* Initialize any external memory */
149 PTR_LA t9, lowlevel_init
153 /* Initialize caches... */
154 PTR_LA t9, mips_cache_reset
158 /* ... and enable them */
159 li t0, CONFIG_SYS_MIPS_CACHE_MODE
163 /* Set up temporary stack */
165 PTR_LI t1, CONFIG_SYS_INIT_SP_ADDR
166 and sp, t1, t0 # force 16 byte alignment
168 sp, sp, GD_SIZE # reserve space for gd
169 and sp, sp, t0 # force 16 byte alignment
170 move k0, sp # save gd pointer
171 #ifdef CONFIG_SYS_MALLOC_F_LEN
172 li t2, CONFIG_SYS_MALLOC_F_LEN
174 sp, sp, t2 # reserve space for early malloc
175 and sp, sp, t0 # force 16 byte alignment
184 PTR_ADDIU t0, PTRSIZE
186 #ifdef CONFIG_SYS_MALLOC_F_LEN
187 PTR_S sp, GD_MALLOC_BASE(k0) # gd->malloc_base offset
190 move a0, zero # a0 <-- boot_flags = 0
191 PTR_LA t9, board_init_f
198 * void relocate_code (addr_sp, gd, addr_moni)
200 * This "function" does not return, instead it continues in RAM
201 * after relocating the monitor code.
205 * a2 = destination address
208 move sp, a0 # set new stack pointer
211 move s0, a1 # save gd in s0
212 move s2, a2 # save destination address in s2
214 PTR_LI t0, CONFIG_SYS_MONITOR_BASE
215 PTR_SUB s1, s2, t0 # s1 <-- relocation offset
218 PTR_L t2, -(3 * PTRSIZE)(t3) # t2 <-- __image_copy_end
221 PTR_ADD gp, s1 # adjust gp
224 * t0 = source address
225 * t1 = target address
226 * t2 = source end address
235 /* If caches were enabled, we would have to flush them here. */
236 PTR_SUB a1, t1, s2 # a1 <-- size
237 PTR_LA t9, flush_cache
239 move a0, s2 # a0 <-- destination address
241 /* Jump to where we've relocated ourselves */
242 PTR_ADDIU t0, s2, in_ram - _start
249 PTR _GLOBAL_OFFSET_TABLE_
254 * Now we want to update GOT.
256 * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
257 * generated by GNU ld. Skip these reserved entries from relocation.
259 PTR_L t3, -(1 * PTRSIZE)(t0) # t3 <-- num_got_entries
260 PTR_L t8, -(2 * PTRSIZE)(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_
261 PTR_ADD t8, s1 # t8 now holds relocated _G_O_T_
262 PTR_ADDIU t8, t8, 2 * PTRSIZE # skipping first two entries
272 PTR_ADDIU t8, PTRSIZE
274 /* Update dynamic relocations */
275 PTR_L t1, -(4 * PTRSIZE)(t0) # t1 <-- __rel_dyn_start
276 PTR_L t2, -(5 * PTRSIZE)(t0) # t2 <-- __rel_dyn_end
278 b 2f # skip first reserved entry
279 PTR_ADDIU t1, 2 * PTRSIZE
282 lw t8, -4(t1) # t8 <-- relocation info
284 PTR_LI t3, MIPS_RELOC
285 bne t8, t3, 2f # skip non-MIPS_RELOC entries
288 PTR_L t3, -(2 * PTRSIZE)(t1) # t3 <-- location to fix up in FLASH
290 PTR_L t8, 0(t3) # t8 <-- original pointer
291 PTR_ADD t8, s1 # t8 <-- adjusted pointer
293 PTR_ADD t3, s1 # t3 <-- location to fix up in RAM
298 PTR_ADDIU t1, 2 * PTRSIZE # each rel.dyn entry is 2*PTRSIZE bytes
303 * GOT is now relocated. Thus __bss_start and __bss_end can be
304 * accessed directly via $gp.
306 PTR_LA t1, __bss_start # t1 <-- __bss_start
307 PTR_LA t2, __bss_end # t2 <-- __bss_end
312 PTR_ADDIU t1, PTRSIZE
314 move a0, s0 # a0 <-- gd
316 PTR_LA t9, board_init_r