2 * Cache-handling routined for MIPS CPUs
4 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
6 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm-offsets.h>
12 #include <asm/regdef.h>
13 #include <asm/mipsregs.h>
14 #include <asm/addrspace.h>
15 #include <asm/cacheops.h>
17 #ifndef CONFIG_SYS_MIPS_CACHE_MODE
18 #define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
21 #define INDEX_BASE CKSEG0
23 .macro f_fill64 dst, offset, val
24 LONG_S \val, (\offset + 0 * LONGSIZE)(\dst)
25 LONG_S \val, (\offset + 1 * LONGSIZE)(\dst)
26 LONG_S \val, (\offset + 2 * LONGSIZE)(\dst)
27 LONG_S \val, (\offset + 3 * LONGSIZE)(\dst)
28 LONG_S \val, (\offset + 4 * LONGSIZE)(\dst)
29 LONG_S \val, (\offset + 5 * LONGSIZE)(\dst)
30 LONG_S \val, (\offset + 6 * LONGSIZE)(\dst)
31 LONG_S \val, (\offset + 7 * LONGSIZE)(\dst)
33 LONG_S \val, (\offset + 8 * LONGSIZE)(\dst)
34 LONG_S \val, (\offset + 9 * LONGSIZE)(\dst)
35 LONG_S \val, (\offset + 10 * LONGSIZE)(\dst)
36 LONG_S \val, (\offset + 11 * LONGSIZE)(\dst)
37 LONG_S \val, (\offset + 12 * LONGSIZE)(\dst)
38 LONG_S \val, (\offset + 13 * LONGSIZE)(\dst)
39 LONG_S \val, (\offset + 14 * LONGSIZE)(\dst)
40 LONG_S \val, (\offset + 15 * LONGSIZE)(\dst)
44 .macro cache_loop curr, end, line_sz, op
45 10: cache \op, 0(\curr)
46 PTR_ADDU \curr, \curr, \line_sz
50 .macro l1_info sz, line_sz, off
54 mfc0 $1, CP0_CONFIG, 1
56 /* detect line size */
57 srl \line_sz, $1, \off + MIPS_CONF1_DL_SHIFT - MIPS_CONF1_DA_SHIFT
58 andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHIFT)
62 sllv \line_sz, \sz, \line_sz
64 /* detect associativity */
65 srl \sz, $1, \off + MIPS_CONF1_DA_SHIFT - MIPS_CONF1_DA_SHIFT
66 andi \sz, \sz, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHIFT)
70 mul \sz, \sz, \line_sz
72 /* detect log32(sets) */
73 srl $1, $1, \off + MIPS_CONF1_DS_SHIFT - MIPS_CONF1_DA_SHIFT
74 andi $1, $1, (MIPS_CONF1_DS >> MIPS_CONF1_DS_SHIFT)
78 /* sz <<= log32(sets) */
88 * mips_cache_reset - low level initialisation of the primary caches
90 * This routine initialises the primary caches to ensure that they have good
91 * parity. It must be called by the ROM before any cached locations are used
92 * to prevent the possibility of data with bad parity being written to memory.
94 * To initialise the instruction cache it is essential that a source of data
95 * with good parity is available. This routine will initialise an area of
96 * memory starting at location zero to be used as a source of parity.
101 LEAF(mips_cache_reset)
102 #ifdef CONFIG_SYS_ICACHE_SIZE
103 li t2, CONFIG_SYS_ICACHE_SIZE
104 li t8, CONFIG_SYS_CACHELINE_SIZE
106 l1_info t2, t8, MIPS_CONF1_IA_SHIFT
109 #ifdef CONFIG_SYS_DCACHE_SIZE
110 li t3, CONFIG_SYS_DCACHE_SIZE
111 li t9, CONFIG_SYS_CACHELINE_SIZE
113 l1_info t3, t9, MIPS_CONF1_DA_SHIFT
116 #ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
118 /* Determine the largest L1 cache size */
119 #if defined(CONFIG_SYS_ICACHE_SIZE) && defined(CONFIG_SYS_DCACHE_SIZE)
120 #if CONFIG_SYS_ICACHE_SIZE > CONFIG_SYS_DCACHE_SIZE
121 li v0, CONFIG_SYS_ICACHE_SIZE
123 li v0, CONFIG_SYS_DCACHE_SIZE
131 * Now clear that much memory starting from zero.
136 f_fill64 a0, -64, zero
139 #endif /* CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD */
142 * The caches are probably in an indeterminate state, so we force good
143 * parity into them by doing an invalidate for each line. If
144 * CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD is set then we'll proceed to
145 * perform a load/fill & a further invalidate for each line, assuming
146 * that the bottom of RAM (having just been cleared) will generate good
147 * parity for the cache.
151 * Initialize the I-cache first,
155 PTR_LI t0, INDEX_BASE
157 /* clear tag to invalidate */
158 cache_loop t0, t1, t8, INDEX_STORE_TAG_I
159 #ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
160 /* fill once, so data field parity is correct */
161 PTR_LI t0, INDEX_BASE
162 cache_loop t0, t1, t8, FILL
163 /* invalidate again - prudent but not strictly neccessary */
164 PTR_LI t0, INDEX_BASE
165 cache_loop t0, t1, t8, INDEX_STORE_TAG_I
169 * then initialize D-cache.
173 PTR_LI t0, INDEX_BASE
176 cache_loop t0, t1, t9, INDEX_STORE_TAG_D
177 #ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
178 /* load from each line (in cached space) */
179 PTR_LI t0, INDEX_BASE
180 2: LONG_L zero, 0(t0)
184 PTR_LI t0, INDEX_BASE
185 cache_loop t0, t1, t9, INDEX_STORE_TAG_D
189 END(mips_cache_reset)
192 * dcache_status - get cache status
194 * RETURNS: 0 - cache disabled; 1 - cache enabled
199 li t1, CONF_CM_UNCACHED
200 andi t0, t0, CONF_CM_CMASK
208 * dcache_disable - disable cache
217 ori t0, t0, CONF_CM_UNCACHED
223 * dcache_enable - enable cache
230 ori t0, CONF_CM_CMASK
231 xori t0, CONF_CM_CMASK
232 ori t0, CONFIG_SYS_MIPS_CACHE_MODE