2 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/addrspace.h>
11 #include <asm/types.h>
12 #include <mach/ath79.h>
13 #include <mach/ar71xx_regs.h>
15 void _machine_restart(void)
20 base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
23 reg = AR71XX_RESET_REG_RESET_MODULE;
24 else if (soc_is_ar724x())
25 reg = AR724X_RESET_REG_RESET_MODULE;
26 else if (soc_is_ar913x())
27 reg = AR913X_RESET_REG_RESET_MODULE;
28 else if (soc_is_ar933x())
29 reg = AR933X_RESET_REG_RESET_MODULE;
30 else if (soc_is_ar934x())
31 reg = AR934X_RESET_REG_RESET_MODULE;
32 else if (soc_is_qca953x())
33 reg = QCA953X_RESET_REG_RESET_MODULE;
34 else if (soc_is_qca955x())
35 reg = QCA955X_RESET_REG_RESET_MODULE;
36 else if (soc_is_qca956x())
37 reg = QCA956X_RESET_REG_RESET_MODULE;
39 puts("Reset register not defined for this SOC\n");
42 setbits_be32(base + reg, AR71XX_RESET_FULL_CHIP);
48 u32 get_bootstrap(void)
53 base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
56 reg = AR933X_RESET_REG_BOOTSTRAP;
57 else if (soc_is_ar934x())
58 reg = AR934X_RESET_REG_BOOTSTRAP;
59 else if (soc_is_qca953x())
60 reg = QCA953X_RESET_REG_BOOTSTRAP;
61 else if (soc_is_qca955x())
62 reg = QCA955X_RESET_REG_BOOTSTRAP;
63 else if (soc_is_qca956x())
64 reg = QCA956X_RESET_REG_BOOTSTRAP;
66 puts("Bootstrap register not defined for this SOC\n");
69 return readl(base + reg);
74 static int eth_init_ar933x(void)
76 void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
78 void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
80 void __iomem *gregs = map_physmem(AR933X_GMAC_BASE, AR933X_GMAC_SIZE,
82 const u32 mask = AR933X_RESET_GE0_MAC | AR933X_RESET_GE0_MDIO |
83 AR933X_RESET_GE1_MAC | AR933X_RESET_GE1_MDIO |
84 AR933X_RESET_ETH_SWITCH;
86 /* Clear MDIO slave EN bit. */
87 clrbits_be32(rregs + AR933X_RESET_REG_BOOTSTRAP, BIT(17));
90 /* Get Atheros S26 PHY out of reset. */
91 clrsetbits_be32(pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG,
95 setbits_be32(rregs + AR933X_RESET_REG_RESET_MODULE, mask);
97 clrbits_be32(rregs + AR933X_RESET_REG_RESET_MODULE, mask);
100 /* Configure AR93xx GMAC register. */
101 clrsetbits_be32(gregs + AR933X_GMAC_REG_ETH_CFG,
102 AR933X_ETH_CFG_MII_GE0_MASTER |
103 AR933X_ETH_CFG_MII_GE0_SLAVE,
104 AR933X_ETH_CFG_MII_GE0_SLAVE);
108 static int eth_init_ar934x(void)
110 void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
112 void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
114 void __iomem *gregs = map_physmem(AR934X_GMAC_BASE, AR934X_GMAC_SIZE,
116 const u32 mask = AR934X_RESET_GE0_MAC | AR934X_RESET_GE0_MDIO |
117 AR934X_RESET_GE1_MAC | AR934X_RESET_GE1_MDIO |
118 AR934X_RESET_ETH_SWITCH_ANALOG;
121 reg = readl(rregs + AR934X_RESET_REG_BOOTSTRAP);
122 if (reg & AR934X_BOOTSTRAP_REF_CLK_40)
123 writel(0x570, pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
125 writel(0x271, pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
126 writel(BIT(26) | BIT(25), pregs + AR934X_PLL_ETH_XMII_CONTROL_REG);
128 setbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
130 clrbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
133 /* Configure AR934x GMAC register. */
134 writel(AR934X_ETH_CFG_RGMII_GMAC0, gregs + AR934X_GMAC_REG_ETH_CFG);
138 int ath79_eth_reset(void)
141 * Un-reset ethernet. DM still doesn't have any notion of reset
142 * framework, so we do it by hand here.
145 return eth_init_ar933x();
147 return eth_init_ar934x();
152 static int usb_reset_ar933x(void __iomem *reset_regs)
154 /* Ungate the USB block */
155 setbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE,
156 AR933X_RESET_USBSUS_OVERRIDE);
158 clrbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE,
159 AR933X_RESET_USB_HOST);
161 clrbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE,
162 AR933X_RESET_USB_PHY);
168 static int usb_reset_ar934x(void __iomem *reset_regs)
170 /* Ungate the USB block */
171 setbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
172 AR934X_RESET_USBSUS_OVERRIDE);
174 clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
175 AR934X_RESET_USB_PHY);
177 clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
178 AR934X_RESET_USB_PHY_ANALOG);
180 clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
181 AR934X_RESET_USB_HOST);
187 int ath79_usb_reset(void)
189 void __iomem *usbc_regs = map_physmem(AR71XX_USB_CTRL_BASE,
190 AR71XX_USB_CTRL_SIZE,
192 void __iomem *reset_regs = map_physmem(AR71XX_RESET_BASE,
196 * Turn on the Buff and Desc swap bits.
197 * NOTE: This write into an undocumented register in mandatory to
198 * get the USB controller operational in BigEndian mode.
200 writel(0xf0000, usbc_regs + AR71XX_USB_CTRL_REG_CONFIG);
203 return usb_reset_ar933x(reset_regs);
205 return usb_reset_ar934x(reset_regs);