2 * Copyright (C) 2012 Andes Technology Corporation
3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
6 * SPDX-License-Identifier: GPL-2.0+
10 #if (!defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF))
11 static inline unsigned long CACHE_SET(unsigned char cache)
14 return 64 << ((GET_ICM_CFG() & ICM_CFG_MSK_ISET) \
17 return 64 << ((GET_DCM_CFG() & DCM_CFG_MSK_DSET) \
21 static inline unsigned long CACHE_WAY(unsigned char cache)
24 return 1 + ((GET_ICM_CFG() & ICM_CFG_MSK_IWAY) \
27 return 1 + ((GET_DCM_CFG() & DCM_CFG_MSK_DWAY) \
31 static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
34 return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
35 >> ICM_CFG_OFF_ISZ) - 1);
37 return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
38 >> DCM_CFG_OFF_DSZ) - 1);
42 #ifndef CONFIG_SYS_ICACHE_OFF
43 void invalidate_icache_all(void)
45 unsigned long end, line_size;
46 line_size = CACHE_LINE_SIZE(ICACHE);
47 end = line_size * CACHE_WAY(ICACHE) * CACHE_SET(ICACHE);
50 __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end));
53 __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end));
56 __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end));
58 __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end));
62 void invalidate_icache_range(unsigned long start, unsigned long end)
64 unsigned long line_size;
66 line_size = CACHE_LINE_SIZE(ICACHE);
69 "\n\tcctl %0, L1I_VA_INVAL"
77 void icache_enable(void)
81 "ori $p0, $p0, 0x01\n\t"
87 void icache_disable(void)
92 "and $p0, $p0, $p1\n\t"
98 int icache_status(void)
104 "andi %0, $p0, 0x01\n\t"
114 void invalidate_icache_all(void)
118 void invalidate_icache_range(unsigned long start, unsigned long end)
122 void icache_enable(void)
126 void icache_disable(void)
130 int icache_status(void)
137 #ifndef CONFIG_SYS_DCACHE_OFF
138 void dcache_wbinval_all(void)
140 unsigned long end, line_size;
141 line_size = CACHE_LINE_SIZE(DCACHE);
142 end = line_size * CACHE_WAY(DCACHE) * CACHE_SET(DCACHE);
145 __asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end));
146 __asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end));
148 __asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end));
149 __asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end));
151 __asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end));
152 __asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end));
154 __asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end));
155 __asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end));
160 void flush_dcache_range(unsigned long start, unsigned long end)
162 unsigned long line_size;
164 line_size = CACHE_LINE_SIZE(DCACHE);
166 while (end > start) {
168 "\n\tcctl %0, L1D_VA_WB"
169 "\n\tcctl %0, L1D_VA_INVAL" : : "r" (start)
175 void invalidate_dcache_range(unsigned long start, unsigned long end)
177 unsigned long line_size;
179 line_size = CACHE_LINE_SIZE(DCACHE);
180 while (end > start) {
182 "\n\tcctl %0, L1D_VA_INVAL" : : "r"(start)
188 void dcache_enable(void)
192 "ori $p0, $p0, 0x02\n\t"
198 void dcache_disable(void)
203 "and $p0, $p0, $p1\n\t"
209 int dcache_status(void)
214 "andi %0, $p0, 0x02\n\t"
223 void dcache_wbinval_all(void)
227 void flush_dcache_range(unsigned long start, unsigned long end)
231 void invalidate_dcache_range(unsigned long start, unsigned long end)
235 void dcache_enable(void)
239 void dcache_disable(void)
243 int dcache_status(void)
251 void flush_dcache_all(void)
253 dcache_wbinval_all();
256 void cache_flush(void)
259 invalidate_icache_all();
263 void flush_cache(unsigned long addr, unsigned long size)
265 flush_dcache_range(addr, addr + size);
266 invalidate_icache_range(addr, addr + size);