2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000-2009 Wolfgang Denk <wd@denx.de>
5 * Copyright Freescale Semiconductor, Inc. 2004, 2006.
7 * SPDX-License-Identifier: GPL-2.0+
9 * Based on the MPC83xx code.
13 * U-Boot - Startup Code for MPC512x based Embedded Boards
16 #include <asm-offsets.h>
20 #define CONFIG_521X 1 /* needed for Linux kernel header files*/
22 #include <asm/immap_512x.h>
23 #include "asm-offsets.h"
25 #include <ppc_asm.tmpl>
28 #include <asm/cache.h>
30 #include <asm/u-boot.h>
33 * Floating Point enable, Machine Check and Recoverable Interr.
37 #define MSR_KERNEL (MSR_FP|MSR_RI)
39 #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
42 /* Macros for manipulating CSx_START/STOP */
43 #define START_REG(start) ((start) >> 16)
44 #define STOP_REG(start, size) (((start) + (size) - 1) >> 16)
47 * Set up GOT: Global Offset Table
49 * Use r12 to access the GOT
52 GOT_ENTRY(_GOT2_TABLE_)
53 GOT_ENTRY(_FIXUP_TABLE_)
56 GOT_ENTRY(_start_of_vectors)
57 GOT_ENTRY(_end_of_vectors)
58 GOT_ENTRY(transfer_to_handler)
62 GOT_ENTRY(__bss_start)
66 * Magic number and version string
68 .long 0x27051956 /* U-Boot Magic Number */
71 .ascii U_BOOT_VERSION_STRING, "\0"
80 /* Start from here after reset/power on */
84 .globl _start_of_vectors
88 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
90 /* Data Storage exception. */
91 STD_EXCEPTION(0x300, DataStorage, UnknownException)
93 /* Instruction Storage exception. */
94 STD_EXCEPTION(0x400, InstStorage, UnknownException)
96 /* External Interrupt exception. */
97 STD_EXCEPTION(0x500, ExtInterrupt, UnknownException)
99 /* Alignment exception. */
102 EXCEPTION_PROLOG(SRR0, SRR1)
107 addi r3,r1,STACK_FRAME_OVERHEAD
108 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
110 /* Program check exception */
113 EXCEPTION_PROLOG(SRR0, SRR1)
114 addi r3,r1,STACK_FRAME_OVERHEAD
115 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
118 /* Floating Point Unit unavailable exception */
119 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
122 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
124 /* Critical interrupt */
125 STD_EXCEPTION(0xa00, Critical, UnknownException)
128 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
130 /* Trace interrupt */
131 STD_EXCEPTION(0xd00, Trace, UnknownException)
133 /* Performance Monitor interrupt */
134 STD_EXCEPTION(0xf00, PerfMon, UnknownException)
136 /* Intruction Translation Miss */
137 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
139 /* Data Load Translation Miss */
140 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
142 /* Data Store Translation Miss */
143 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
145 /* Instruction Address Breakpoint */
146 STD_EXCEPTION(0x1300, InstructionAddrBreakpoint, DebugException)
148 /* System Management interrupt */
149 STD_EXCEPTION(0x1400, SystemMgmtInterrupt, UnknownException)
151 .globl _end_of_vectors
156 /* Save msr contents */
159 /* Set IMMR area to our preferred location */
160 lis r4, CONFIG_DEFAULT_IMMR@h
161 lis r3, CONFIG_SYS_IMMR@h
162 ori r3, r3, CONFIG_SYS_IMMR@l
164 mtspr MBAR, r3 /* IMMRBAR is mirrored into the MBAR SPR (311) */
166 /* Initialise the machine */
170 * Set up Local Access Windows:
172 * 1) Boot/CS0 (boot FLASH)
173 * 2) On-chip SRAM (initial stack purposes)
176 /* Boot CS/CS0 window range */
177 lis r3, CONFIG_SYS_IMMR@h
178 ori r3, r3, CONFIG_SYS_IMMR@l
180 lis r4, START_REG(CONFIG_SYS_FLASH_BASE)
181 ori r4, r4, STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE)
185 * The SRAM window has a fixed size (256K), so only the start address
188 lis r4, START_REG(CONFIG_SYS_SRAM_BASE) & 0xff00
192 * According to MPC5121e RM, configuring local access windows should
193 * be followed by a dummy read of the config register that was
194 * modified last and an isync
200 * Set configuration of the Boot/CS0, the SRAM window does not have a
201 * config register so no params can be set for it
203 lis r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@h
204 ori r3, r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@l
206 lis r4, CONFIG_SYS_CS0_CFG@h
207 ori r4, r4, CONFIG_SYS_CS0_CFG@l
208 stw r4, CS0_CONFIG(r3)
210 /* Master enable all CS's */
212 ori r4, r4, CS_CTRL_ME@l
215 lis r4, (CONFIG_SYS_MONITOR_BASE)@h
216 ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l
217 addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
222 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
223 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
225 li r0, 0 /* Make room for stack frame header and */
226 stwu r0, -4(r1) /* clear final stack frame so that */
227 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
229 /* let the C-code set up the rest */
231 /* Be careful to keep code relocatable & stack humble */
232 /*------------------------------------------------------*/
234 GET_GOT /* initialize GOT access */
237 lis r3, CONFIG_SYS_IMMR@h
238 /* run low-level CPU init code (in Flash) */
241 /* run 1st part of board init code (in Flash) */
244 /* NOTREACHED - board_init_f() does not return */
247 * This code finishes saving the registers to the exception frame
248 * and jumps to the appropriate handler for the exception.
249 * Register r21 is pointer into trap frame, r1 has new stack pointer.
251 .globl transfer_to_handler
262 andi. r24,r23,0x3f00 /* get vector offset */
266 lwz r24,0(r23) /* virtual address of handler */
267 lwz r23,4(r23) /* where to go when done */
272 rfi /* jump to handler, enable MMU */
275 mfmsr r28 /* Disable interrupts */
279 SYNC /* Some chip revs need this... */
294 lwz r2,_NIP(r1) /* Restore environment */
305 * This code initialises the machine, it expects original MSR contents to be in r5.
308 /* Initialize machine status; enable machine check interrupt */
309 /*-----------------------------------------------------------*/
311 li r3, MSR_KERNEL /* Set ME and RI flags */
312 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit */
314 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE, BE bits */
318 mtspr SRR1, r3 /* Mirror current MSR state in SRR1 */
320 lis r3, CONFIG_SYS_IMMR@h
322 #if defined(CONFIG_WATCHDOG)
323 /* Initialise the watchdog and reset it */
324 /*--------------------------------------*/
325 lis r4, CONFIG_SYS_WATCHDOG_VALUE
326 ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
336 /* Disable the watchdog */
337 /*----------------------*/
340 * Check to see if it's enabled for disabling: once disabled by s/w
341 * it's not possible to re-enable it
348 #endif /* CONFIG_WATCHDOG */
350 /* Initialize the Hardware Implementation-dependent Registers */
351 /* HID0 also contains cache control */
352 /*------------------------------------------------------*/
353 lis r3, CONFIG_SYS_HID0_INIT@h
354 ori r3, r3, CONFIG_SYS_HID0_INIT@l
358 lis r3, CONFIG_SYS_HID0_FINAL@h
359 ori r3, r3, CONFIG_SYS_HID0_FINAL@l
363 lis r3, CONFIG_SYS_HID2@h
364 ori r3, r3, CONFIG_SYS_HID2@l
373 * Note: requires that all cache bits in
374 * HID0 are in the low half word.
381 ori r4, r4, HID0_ILOCK
383 ori r4, r3, HID0_ICFI
385 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
387 mtspr HID0, r3 /* clears invalidate */
390 .globl icache_disable
394 ori r4, r4, HID0_ICE|HID0_ILOCK
396 ori r4, r3, HID0_ICFI
398 mtspr HID0, r4 /* sets invalidate, clears enable and lock*/
400 mtspr HID0, r3 /* clears invalidate */
406 rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
412 li r5, HID0_DCFI|HID0_DLOCK
414 mtspr HID0, r3 /* no invalidate, unlock */
416 ori r5, r3, HID0_DCFI
417 mtspr HID0, r5 /* enable + invalidate */
418 mtspr HID0, r3 /* enable */
422 .globl dcache_disable
426 ori r4, r4, HID0_DCE|HID0_DLOCK
430 mtspr HID0, r4 /* sets invalidate, clears enable and lock */
432 mtspr HID0, r3 /* clears invalidate */
438 rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
451 /*-------------------------------------------------------------------*/
454 * void relocate_code (addr_sp, gd, addr_moni)
456 * This "function" does not return, instead it continues in RAM
457 * after relocating the monitor code.
461 * r5 = length in bytes
466 mr r1, r3 /* Set new stack pointer */
467 mr r9, r4 /* Save copy of Global Data pointer */
468 mr r10, r5 /* Save copy of Destination Address */
471 mr r3, r5 /* Destination Address */
472 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
473 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
474 lwz r5, GOT(__init_end)
476 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
481 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE)
482 * + Destination Address
488 /* First our own GOT */
490 /* then the one used by the C code */
499 beq cr1,4f /* In place copy is not necessary */
500 beq 7f /* Protect against 0 count */
529 2: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */
537 * Now flush the cache: note that we must start from a cache aligned
538 * address. Otherwise we might miss one cache line.
542 beq 7f /* Always flush prefetch queue in any case */
550 sync /* Wait for all dcbst to complete on bus */
556 7: sync /* Wait for all icbi to complete on bus */
560 * We are done. Do not return, instead branch to second part of board
561 * initialization, now running from RAM.
563 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
569 * Relocation Function, r12 point to got2+0x8000
571 * Adjust got2 pointers, no need to check for 0, this code
572 * already puts a few entries in the table.
574 li r0,__got2_entries@sectoff@l
575 la r3,GOT(_GOT2_TABLE_)
576 lwz r11,GOT(_GOT2_TABLE_)
588 * Now adjust the fixups and the pointers to the fixups
589 * in case we need to move ourselves again.
591 li r0,__fixup_entries@sectoff@l
592 lwz r3,GOT(_FIXUP_TABLE_)
608 * Now clear BSS segment
610 lwz r3,GOT(__bss_start)
611 lwz r4,GOT(__bss_end)
623 mr r3, r9 /* Global Data pointer */
624 mr r4, r10 /* Destination Address */
628 * Copy exception vector code to low memory
631 * r7: source address, r8: end address, r9: target address
635 mflr r4 /* save link register */
638 lwz r8, GOT(_end_of_vectors)
640 li r9, 0x100 /* reset vector at 0x100 */
643 bgelr /* return if r7>=r8 - just in case */
653 * relocate `hdlr' and `int_return' entries
655 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
656 li r8, Alignment - _start + EXC_OFF_SYS_RESET
659 addi r7, r7, 0x100 /* next exception vector */
663 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
666 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
669 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
670 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
673 addi r7, r7, 0x100 /* next exception vector */
677 li r7, .L_Trace - _start + EXC_OFF_SYS_RESET
678 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
681 addi r7, r7, 0x100 /* next exception vector */
685 mfmsr r3 /* now that the vectors have */
686 lis r7, MSR_IP@h /* relocated into low memory */
687 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
688 andc r3, r3, r7 /* (if it was on) */
689 SYNC /* Some chip revs need this... */
693 mtlr r4 /* restore link register */