2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000 - 2003 Wolfgang Denk <wd@denx.de>
6 * SPDX-License-Identifier: GPL-2.0+
10 * U-Boot - Startup Code for MPC5xxx CPUs
12 #include <asm-offsets.h>
17 #include <ppc_asm.tmpl>
20 #include <asm/cache.h>
22 #include <asm/u-boot.h>
24 /* We don't want the MMU yet.
27 /* Floating Point enable, Machine Check and Recoverable Interr. */
29 #define MSR_KERNEL (MSR_FP|MSR_RI)
31 #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
34 #ifndef CONFIG_SPL_BUILD
36 * Set up GOT: Global Offset Table
38 * Use r12 to access the GOT
41 GOT_ENTRY(_GOT2_TABLE_)
42 GOT_ENTRY(_FIXUP_TABLE_)
45 GOT_ENTRY(_start_of_vectors)
46 GOT_ENTRY(_end_of_vectors)
47 GOT_ENTRY(transfer_to_handler)
51 GOT_ENTRY(__bss_start)
61 .ascii U_BOOT_VERSION_STRING, "\0"
71 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
73 * This is the entry of the real U-Boot from a board port
74 * that supports SPL booting on the MPC5200. We only need
75 * to call board_init_f() here. Everything else has already
76 * been done in the SPL u-boot version.
78 GET_GOT /* initialize GOT access */
81 * The GD (global data) struct needs to get cleared. Lets do
82 * this by calling memset().
83 * This function is called when the platform is build with SPL
84 * support from the main (full-blown) U-Boot. And the GD needs
85 * to get cleared (again) so that the following generic
86 * board support code, defined via CONFIG_SYS_GENERIC_BOARD,
87 * initializes all variables correctly.
89 mr r3, r2 /* parameter 1: GD pointer */
90 li r4,0 /* parameter 2: value to fill */
91 li r5,GD_SIZE /* parameter 3: count */
94 bl board_init_f /* run 1st part of board init code (in Flash)*/
95 /* NOTREACHED - board_init_f() does not return */
97 mfmsr r5 /* save msr contents */
99 /* Move CSBoot and adjust instruction pointer */
100 /*--------------------------------------------------------------*/
102 #if defined(CONFIG_SYS_LOWBOOT)
103 # if defined(CONFIG_SYS_RAMBOOT)
104 # error CONFIG_SYS_LOWBOOT is incompatible with CONFIG_SYS_RAMBOOT
105 # endif /* CONFIG_SYS_RAMBOOT */
106 lis r4, CONFIG_SYS_DEFAULT_MBAR@h
107 lis r3, START_REG(CONFIG_SYS_BOOTCS_START)@h
108 ori r3, r3, START_REG(CONFIG_SYS_BOOTCS_START)@l
109 stw r3, 0x4(r4) /* CS0 start */
110 lis r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@h
111 ori r3, r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@l
112 stw r3, 0x8(r4) /* CS0 stop */
114 ori r3, r3, 0x02010000@l
115 stw r3, 0x54(r4) /* CS0 and Boot enable */
117 lis r3, lowboot_reentry@h /* jump from bootlow address space (0x0000xxxx) */
118 ori r3, r3, lowboot_reentry@l /* to the address space the linker used */
123 lis r3, START_REG(CONFIG_SYS_BOOTCS_START)@h
124 ori r3, r3, START_REG(CONFIG_SYS_BOOTCS_START)@l
125 stw r3, 0x4c(r4) /* Boot start */
126 lis r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@h
127 ori r3, r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@l
128 stw r3, 0x50(r4) /* Boot stop */
130 ori r3, r3, 0x02000001@l
131 stw r3, 0x54(r4) /* Boot enable, CS0 disable */
132 #endif /* CONFIG_SYS_LOWBOOT */
134 #if defined(CONFIG_SYS_DEFAULT_MBAR) && !defined(CONFIG_SYS_RAMBOOT)
135 lis r3, CONFIG_SYS_MBAR@h
136 ori r3, r3, CONFIG_SYS_MBAR@l
137 /* MBAR is mirrored into the MBAR SPR */
139 rlwinm r3, r3, 16, 16, 31
140 lis r4, CONFIG_SYS_DEFAULT_MBAR@h
142 #endif /* CONFIG_SYS_DEFAULT_MBAR */
144 /* Initialise the MPC5xxx processor core */
145 /*--------------------------------------------------------------*/
149 /* initialize some things that are hard to access from C */
150 /*--------------------------------------------------------------*/
152 /* set up stack in on-chip SRAM */
153 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
154 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
155 ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET
156 li r0, 0 /* Make room for stack frame header and */
157 stwu r0, -4(r1) /* clear final stack frame so that */
158 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
160 /* let the C-code set up the rest */
162 /* Be careful to keep code relocatable ! */
163 /*--------------------------------------------------------------*/
165 #ifndef CONFIG_SPL_BUILD
166 GET_GOT /* initialize GOT access */
170 bl cpu_init_f /* run low-level CPU init code (in Flash)*/
172 bl board_init_f /* run 1st part of board init code (in Flash)*/
174 /* NOTREACHED - board_init_f() does not return */
177 #ifndef CONFIG_SPL_BUILD
182 .globl _start_of_vectors
186 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
188 /* Data Storage exception. */
189 STD_EXCEPTION(0x300, DataStorage, UnknownException)
191 /* Instruction Storage exception. */
192 STD_EXCEPTION(0x400, InstStorage, UnknownException)
194 /* External Interrupt exception. */
195 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
197 /* Alignment exception. */
200 EXCEPTION_PROLOG(SRR0, SRR1)
205 addi r3,r1,STACK_FRAME_OVERHEAD
206 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
208 /* Program check exception */
211 EXCEPTION_PROLOG(SRR0, SRR1)
212 addi r3,r1,STACK_FRAME_OVERHEAD
213 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
216 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
218 /* I guess we could implement decrementer, and may have
219 * to someday for timekeeping.
221 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
223 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
224 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
225 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
226 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
228 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
229 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
231 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
232 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
233 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
237 * This exception occurs when the program counter matches the
238 * Instruction Address Breakpoint Register (IABR).
240 * I want the cpu to halt if this occurs so I can hunt around
241 * with the debugger and look at things.
243 * When DEBUG is defined, both machine check enable (in the MSR)
244 * and checkstop reset enable (in the reset mode register) are
245 * turned off and so a checkstop condition will result in the cpu
248 * I force the cpu into a checkstop condition by putting an illegal
249 * instruction here (at least this is the theory).
251 * well - that didnt work, so just do an infinite loop!
255 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
257 STD_EXCEPTION(0x1400, SMI, UnknownException)
259 STD_EXCEPTION(0x1500, Trap_15, UnknownException)
260 STD_EXCEPTION(0x1600, Trap_16, UnknownException)
261 STD_EXCEPTION(0x1700, Trap_17, UnknownException)
262 STD_EXCEPTION(0x1800, Trap_18, UnknownException)
263 STD_EXCEPTION(0x1900, Trap_19, UnknownException)
264 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
265 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
266 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
267 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
268 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
269 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
270 STD_EXCEPTION(0x2000, Trap_20, UnknownException)
271 STD_EXCEPTION(0x2100, Trap_21, UnknownException)
272 STD_EXCEPTION(0x2200, Trap_22, UnknownException)
273 STD_EXCEPTION(0x2300, Trap_23, UnknownException)
274 STD_EXCEPTION(0x2400, Trap_24, UnknownException)
275 STD_EXCEPTION(0x2500, Trap_25, UnknownException)
276 STD_EXCEPTION(0x2600, Trap_26, UnknownException)
277 STD_EXCEPTION(0x2700, Trap_27, UnknownException)
278 STD_EXCEPTION(0x2800, Trap_28, UnknownException)
279 STD_EXCEPTION(0x2900, Trap_29, UnknownException)
280 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
281 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
282 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
283 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
284 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
285 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
288 .globl _end_of_vectors
294 * This code finishes saving the registers to the exception frame
295 * and jumps to the appropriate handler for the exception.
296 * Register r21 is pointer into trap frame, r1 has new stack pointer.
298 .globl transfer_to_handler
309 andi. r24,r23,0x3f00 /* get vector offset */
313 lwz r24,0(r23) /* virtual address of handler */
314 lwz r23,4(r23) /* where to go when done */
319 rfi /* jump to handler, enable MMU */
322 mfmsr r28 /* Disable interrupts */
326 SYNC /* Some chip revs need this... */
341 lwz r2,_NIP(r1) /* Restore environment */
350 #endif /* CONFIG_SPL_BUILD */
353 * This code initialises the MPC5xxx processor core
354 * (conforms to PowerPC 603e spec)
355 * Note: expects original MSR contents to be in r5.
361 /* Initialize machine status; enable machine check interrupt */
362 /*--------------------------------------------------------------*/
364 li r3, MSR_KERNEL /* Set ME and RI flags */
365 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */
367 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
369 SYNC /* Some chip revs need this... */
372 mtspr SRR1, r3 /* Make SRR1 match MSR */
374 /* Initialize the Hardware Implementation-dependent Registers */
375 /* HID0 also contains cache control */
376 /*--------------------------------------------------------------*/
378 lis r3, CONFIG_SYS_HID0_INIT@h
379 ori r3, r3, CONFIG_SYS_HID0_INIT@l
383 lis r3, CONFIG_SYS_HID0_FINAL@h
384 ori r3, r3, CONFIG_SYS_HID0_FINAL@l
388 /* clear all BAT's */
389 /*--------------------------------------------------------------*/
426 /* invalidate all tlb's */
428 /* From the 603e User Manual: "The 603e provides the ability to */
429 /* invalidate a TLB entry. The TLB Invalidate Entry (tlbie) */
430 /* instruction invalidates the TLB entry indexed by the EA, and */
431 /* operates on both the instruction and data TLBs simultaneously*/
432 /* invalidating four TLB entries (both sets in each TLB). The */
433 /* index corresponds to bits 15-19 of the EA. To invalidate all */
434 /* entries within both TLBs, 32 tlbie instructions should be */
435 /* issued, incrementing this field by one each time." */
437 /* "Note that the tlbia instruction is not implemented on the */
440 /* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 */
441 /* incrementing by 0x1000 each time. The code below is sort of */
442 /* based on code in "flush_tlbs" from arch/powerpc/kernel/head.S */
444 /*--------------------------------------------------------------*/
455 /*--------------------------------------------------------------*/
461 * Note: requires that all cache bits in
462 * HID0 are in the low half word.
469 ori r4, r4, HID0_ILOCK
471 ori r4, r3, HID0_ICFI
473 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
475 mtspr HID0, r3 /* clears invalidate */
478 .globl icache_disable
482 ori r4, r4, HID0_ICE|HID0_ILOCK
484 ori r4, r3, HID0_ICFI
486 mtspr HID0, r4 /* sets invalidate, clears enable and lock */
488 mtspr HID0, r3 /* clears invalidate */
494 rlwinm r3, r3, HID0_ICE_BITPOS + 1, 31, 31
502 ori r4, r4, HID0_DLOCK
506 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
508 mtspr HID0, r3 /* clears invalidate */
511 .globl dcache_disable
515 ori r4, r4, HID0_DCE|HID0_DLOCK
519 mtspr HID0, r4 /* sets invalidate, clears enable and lock */
521 mtspr HID0, r3 /* clears invalidate */
527 rlwinm r3, r3, HID0_DCE_BITPOS + 1, 31, 31
540 #ifndef CONFIG_SPL_BUILD
541 /*------------------------------------------------------------------------------*/
544 * void relocate_code (addr_sp, gd, addr_moni)
546 * This "function" does not return, instead it continues in RAM
547 * after relocating the monitor code.
551 * r5 = length in bytes
556 mr r1, r3 /* Set new stack pointer */
557 mr r9, r4 /* Save copy of Global Data pointer */
558 mr r10, r5 /* Save copy of Destination Address */
561 mr r3, r5 /* Destination Address */
562 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
563 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
564 lwz r5, GOT(__init_end)
566 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
571 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
577 /* First our own GOT */
579 /* then the one used by the C code */
589 beq cr1,4f /* In place copy is not necessary */
590 beq 7f /* Protect against 0 count */
609 * Now flush the cache: note that we must start from a cache aligned
610 * address. Otherwise we might miss one cache line.
614 beq 7f /* Always flush prefetch queue in any case */
617 mfspr r7,HID0 /* don't do dcbst if dcache is disabled */
618 rlwinm r7,r7,HID0_DCE_BITPOS+1,31,31
626 sync /* Wait for all dcbst to complete on bus */
627 9: mfspr r7,HID0 /* don't do icbi if icache is disabled */
628 rlwinm r7,r7,HID0_ICE_BITPOS+1,31,31
636 7: sync /* Wait for all icbi to complete on bus */
640 * We are done. Do not return, instead branch to second part of board
641 * initialization, now running from RAM.
644 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
651 * Relocation Function, r12 point to got2+0x8000
653 * Adjust got2 pointers, no need to check for 0, this code
654 * already puts a few entries in the table.
656 li r0,__got2_entries@sectoff@l
657 la r3,GOT(_GOT2_TABLE_)
658 lwz r11,GOT(_GOT2_TABLE_)
670 * Now adjust the fixups and the pointers to the fixups
671 * in case we need to move ourselves again.
673 li r0,__fixup_entries@sectoff@l
674 lwz r3,GOT(_FIXUP_TABLE_)
690 * Now clear BSS segment
692 lwz r3,GOT(__bss_start)
693 lwz r4,GOT(__bss_end)
706 mr r3, r9 /* Global Data pointer */
707 mr r4, r10 /* Destination Address */
711 * Copy exception vector code to low memory
714 * r7: source address, r8: end address, r9: target address
718 mflr r4 /* save link register */
721 lwz r8, GOT(_end_of_vectors)
723 li r9, 0x100 /* reset vector always at 0x100 */
726 bgelr /* return if r7>=r8 - just in case */
736 * relocate `hdlr' and `int_return' entries
738 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
739 li r8, Alignment - _start + EXC_OFF_SYS_RESET
742 addi r7, r7, 0x100 /* next exception vector */
746 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
749 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
752 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
753 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
756 addi r7, r7, 0x100 /* next exception vector */
760 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
761 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
764 addi r7, r7, 0x100 /* next exception vector */
768 mfmsr r3 /* now that the vectors have */
769 lis r7, MSR_IP@h /* relocated into low memory */
770 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
771 andc r3, r3, r7 /* (if it was on) */
772 SYNC /* Some chip revs need this... */
776 mtlr r4 /* restore link register */
779 #endif /* CONFIG_SPL_BUILD */