2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de>
6 * SPDX-License-Identifier: GPL-2.0+
10 * U-Boot - Startup Code for MPC8260 PowerPC based Embedded Boards
12 #include <asm-offsets.h>
17 #define CONFIG_8260 1 /* needed for Linux kernel header files */
18 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
20 #include <ppc_asm.tmpl>
23 #include <asm/cache.h>
25 #include <asm/u-boot.h>
27 /* We don't want the MMU yet.
30 /* Floating Point enable, Machine Check and Recoverable Interr. */
32 #define MSR_KERNEL (MSR_FP|MSR_RI)
34 #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
38 * Set up GOT: Global Offset Table
40 * Use r12 to access the GOT
43 GOT_ENTRY(_GOT2_TABLE_)
44 GOT_ENTRY(_FIXUP_TABLE_)
47 GOT_ENTRY(_start_of_vectors)
48 GOT_ENTRY(_end_of_vectors)
49 GOT_ENTRY(transfer_to_handler)
53 GOT_ENTRY(__bss_start)
54 #if defined(CONFIG_HYMOD)
55 GOT_ENTRY(environment)
60 * Version string - must be in data segment because MPC8260 uses the first
61 * 256 bytes for the Hard Reset Configuration Word table (see below).
62 * Similarly, can't have the U-Boot Magic Number as the first thing in
63 * the image - don't know how this will affect the image tools, but I guess
69 .ascii U_BOOT_VERSION_STRING, "\0"
72 * Hard Reset Configuration Word (HRCW) table
74 * The Hard Reset Configuration Word (HRCW) sets a number of useful things
75 * such as whether there is an external memory controller, whether the
76 * PowerPC core is disabled (i.e. only the communications processor is
77 * active, accessed by another CPU on the bus), whether using external
78 * arbitration, external bus mode, boot port size, core initial prefix,
79 * internal space base, boot memory space, etc.
81 * These things dictate where the processor begins execution, where the
82 * boot ROM appears in memory, the memory controller setup when access
83 * boot ROM, etc. The HRCW is *extremely* important.
85 * The HRCW is read from the bus during reset. One CPU on the bus will
86 * be a hard reset configuration master, any others will be hard reset
87 * configuration slaves. The master reads eight HRCWs from flash during
88 * reset - the first it uses for itself, the other 7 it communicates to
89 * up to 7 configuration slaves by some complicated mechanism, which is
90 * not really important here.
92 * The configuration master performs 32 successive reads starting at address
93 * 0 and incrementing by 8 each read (i.e. on 64 bit boundaries) but only 8
94 * bits is read, and always from byte lane D[0-7] (so that port size of the
95 * boot device does not matter). The first four reads form the 32 bit HRCW
96 * for the master itself. The second four reads form the HRCW for the first
97 * slave, and so on, up to seven slaves. The 32 bit HRCW is formed by
98 * concatenating the four bytes, with the first read placed in byte 0 (the
99 * most significant byte), and so on with the fourth read placed in byte 3
100 * (the least significant byte).
102 #define _HRCW_TABLE_ENTRY(w) \
103 .fill 8,1,(((w)>>24)&0xff); \
104 .fill 8,1,(((w)>>16)&0xff); \
105 .fill 8,1,(((w)>> 8)&0xff); \
106 .fill 8,1,(((w) )&0xff)
110 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_MASTER)
111 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE1)
112 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE2)
113 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE3)
114 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE4)
115 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE5)
116 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE6)
117 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE7)
119 * After configuration, a system reset exception is executed using the
120 * vector at offset 0x100 relative to the base set by MSR[IP]. If MSR[IP]
121 * is 0, the base address is 0x00000000. If MSR[IP] is 1, the base address
122 * is 0xfff00000. In the case of a Power On Reset or Hard Reset, the value
123 * of MSR[IP] is determined by the CIP field in the HRCW.
125 * Other bits in the HRCW set up the Base Address and Port Size in BR0.
126 * This determines the location of the boot ROM (flash or EPROM) in the
127 * processor's address space at boot time. As long as the HRCW is set up
128 * so that we eventually end up executing the code below when the processor
129 * executes the reset exception, the actual values used should not matter.
131 * Once we have got here, the address mask in OR0 is cleared so that the
132 * bottom 32K of the boot ROM is effectively repeated all throughout the
133 * processor's address space, after which we can jump to the absolute
134 * address at which the boot ROM was linked at compile time, and proceed
135 * to initialise the memory controller without worrying if the rug will be
136 * pulled out from under us, so to speak (it will be fine as long as we
137 * configure BR0 with the same boot ROM link address).
139 . = EXC_OFF_SYS_RESET
143 #if defined(CONFIG_MPC8260ADS) && defined(CONFIG_SYS_DEFAULT_IMMR)
144 lis r3, CONFIG_SYS_DEFAULT_IMMR@h
148 rlwinm r4, r4, 0, 8, 5
154 #endif /* CONFIG_MPC8260ADS && CONFIG_SYS_DEFAULT_IMMR */
156 mfmsr r5 /* save msr contents */
158 #if defined(CONFIG_COGENT)
159 /* this is what the cogent EPROM does */
164 #endif /* CONFIG_COGENT */
166 #if defined(CONFIG_SYS_DEFAULT_IMMR)
167 lis r3, CONFIG_SYS_IMMR@h
168 ori r3, r3, CONFIG_SYS_IMMR@l
169 lis r4, CONFIG_SYS_DEFAULT_IMMR@h
171 #endif /* CONFIG_SYS_DEFAULT_IMMR */
173 /* Initialise the MPC8260 processor core */
174 /*--------------------------------------------------------------*/
178 #ifndef CONFIG_SYS_RAMBOOT
179 /* When booting from ROM (Flash or EPROM), clear the */
180 /* Address Mask in OR0 so ROM appears everywhere */
181 /*--------------------------------------------------------------*/
183 lis r3, (CONFIG_SYS_IMMR+IM_REGBASE)@h
189 /* Calculate absolute address in FLASH and jump there */
190 /*--------------------------------------------------------------*/
192 lis r3, CONFIG_SYS_MONITOR_BASE@h
193 ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
194 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
199 #endif /* CONFIG_SYS_RAMBOOT */
201 /* initialize some things that are hard to access from C */
202 /*--------------------------------------------------------------*/
204 lis r3, CONFIG_SYS_IMMR@h /* set up stack in internal DPRAM */
205 ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET
206 li r0, 0 /* Make room for stack frame header and */
207 stwu r0, -4(r1) /* clear final stack frame so that */
208 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
210 /* let the C-code set up the rest */
212 /* Be careful to keep code relocatable ! */
213 /*--------------------------------------------------------------*/
215 GET_GOT /* initialize GOT access */
218 bl cpu_init_f /* run low-level CPU init code (in Flash)*/
221 bl init_debug /* set up debugging stuff */
224 bl board_init_f /* run 1st part of board init code (in Flash)*/
226 /* NOTREACHED - board_init_f() does not return */
232 .globl _start_of_vectors
236 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
238 /* Data Storage exception. */
239 STD_EXCEPTION(0x300, DataStorage, UnknownException)
241 /* Instruction Storage exception. */
242 STD_EXCEPTION(0x400, InstStorage, UnknownException)
244 /* External Interrupt exception. */
245 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
247 /* Alignment exception. */
250 EXCEPTION_PROLOG(SRR0, SRR1)
255 addi r3,r1,STACK_FRAME_OVERHEAD
256 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
258 /* Program check exception */
261 EXCEPTION_PROLOG(SRR0, SRR1)
262 addi r3,r1,STACK_FRAME_OVERHEAD
263 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
266 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
268 /* I guess we could implement decrementer, and may have
269 * to someday for timekeeping.
271 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
273 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
274 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
275 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
276 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
278 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
279 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
281 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
282 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
283 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
287 * This exception occurs when the program counter matches the
288 * Instruction Address Breakpoint Register (IABR).
290 * I want the cpu to halt if this occurs so I can hunt around
291 * with the debugger and look at things.
293 * When DEBUG is defined, both machine check enable (in the MSR)
294 * and checkstop reset enable (in the reset mode register) are
295 * turned off and so a checkstop condition will result in the cpu
298 * I force the cpu into a checkstop condition by putting an illegal
299 * instruction here (at least this is the theory).
301 * well - that didnt work, so just do an infinite loop!
305 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
307 STD_EXCEPTION(0x1400, SMI, UnknownException)
309 STD_EXCEPTION(0x1500, Trap_15, UnknownException)
310 STD_EXCEPTION(0x1600, Trap_16, UnknownException)
311 STD_EXCEPTION(0x1700, Trap_17, UnknownException)
312 STD_EXCEPTION(0x1800, Trap_18, UnknownException)
313 STD_EXCEPTION(0x1900, Trap_19, UnknownException)
314 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
315 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
316 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
317 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
318 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
319 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
320 STD_EXCEPTION(0x2000, Trap_20, UnknownException)
321 STD_EXCEPTION(0x2100, Trap_21, UnknownException)
322 STD_EXCEPTION(0x2200, Trap_22, UnknownException)
323 STD_EXCEPTION(0x2300, Trap_23, UnknownException)
324 STD_EXCEPTION(0x2400, Trap_24, UnknownException)
325 STD_EXCEPTION(0x2500, Trap_25, UnknownException)
326 STD_EXCEPTION(0x2600, Trap_26, UnknownException)
327 STD_EXCEPTION(0x2700, Trap_27, UnknownException)
328 STD_EXCEPTION(0x2800, Trap_28, UnknownException)
329 STD_EXCEPTION(0x2900, Trap_29, UnknownException)
330 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
331 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
332 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
333 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
334 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
335 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
338 .globl _end_of_vectors
344 * This code finishes saving the registers to the exception frame
345 * and jumps to the appropriate handler for the exception.
346 * Register r21 is pointer into trap frame, r1 has new stack pointer.
348 .globl transfer_to_handler
359 andi. r24,r23,0x3f00 /* get vector offset */
363 lwz r24,0(r23) /* virtual address of handler */
364 lwz r23,4(r23) /* where to go when done */
369 rfi /* jump to handler, enable MMU */
372 mfmsr r28 /* Disable interrupts */
376 SYNC /* Some chip revs need this... */
391 lwz r2,_NIP(r1) /* Restore environment */
401 #if defined(CONFIG_COGENT)
404 * This code initialises the MPC8260 processor core
405 * (conforms to PowerPC 603e spec)
408 .globl cogent_init_8260
411 /* Taken from page 14 of CMA282 manual */
412 /*--------------------------------------------------------------*/
414 lis r4, (CONFIG_SYS_IMMR+IM_REGBASE)@h
415 lis r3, CONFIG_SYS_IMMR@h
416 stw r3, IM_IMMR@l(r4)
417 lwz r3, IM_IMMR@l(r4)
419 lis r3, CONFIG_SYS_SYPCR@h
420 ori r3, r3, CONFIG_SYS_SYPCR@l
421 stw r3, IM_SYPCR@l(r4)
422 lwz r3, IM_SYPCR@l(r4)
424 lis r3, CONFIG_SYS_SCCR@h
425 ori r3, r3, CONFIG_SYS_SCCR@l
426 stw r3, IM_SCCR@l(r4)
427 lwz r3, IM_SCCR@l(r4)
430 /* the rest of this was disassembled from the */
431 /* EPROM code that came with my CMA282 CPU module */
432 /*--------------------------------------------------------------*/
446 /*--------------------------------------------------------------*/
450 #endif /* CONFIG_COGENT */
453 * This code initialises the MPC8260 processor core
454 * (conforms to PowerPC 603e spec)
455 * Note: expects original MSR contents to be in r5.
458 .globl init_8260_core
461 /* Initialize machine status; enable machine check interrupt */
462 /*--------------------------------------------------------------*/
464 li r3, MSR_KERNEL /* Set ME and RI flags */
465 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */
467 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
469 SYNC /* Some chip revs need this... */
472 mtspr SRR1, r3 /* Make SRR1 match MSR */
474 /* Initialise the SYPCR early, and reset the watchdog (if req) */
475 /*--------------------------------------------------------------*/
477 lis r3, (CONFIG_SYS_IMMR+IM_REGBASE)@h
478 #if !defined(CONFIG_COGENT)
479 lis r4, CONFIG_SYS_SYPCR@h
480 ori r4, r4, CONFIG_SYS_SYPCR@l
481 stw r4, IM_SYPCR@l(r3)
482 #endif /* !CONFIG_COGENT */
483 #if defined(CONFIG_WATCHDOG)
484 li r4, 21868 /* = 0x556c */
485 sth r4, IM_SWSR@l(r3)
486 li r4, -21959 /* = 0xaa39 */
487 sth r4, IM_SWSR@l(r3)
488 #endif /* CONFIG_WATCHDOG */
490 /* Initialize the Hardware Implementation-dependent Registers */
491 /* HID0 also contains cache control */
492 /*--------------------------------------------------------------*/
494 lis r3, CONFIG_SYS_HID0_INIT@h
495 ori r3, r3, CONFIG_SYS_HID0_INIT@l
499 lis r3, CONFIG_SYS_HID0_FINAL@h
500 ori r3, r3, CONFIG_SYS_HID0_FINAL@l
504 lis r3, CONFIG_SYS_HID2@h
505 ori r3, r3, CONFIG_SYS_HID2@l
508 /* clear all BAT's */
509 /*--------------------------------------------------------------*/
530 /* invalidate all tlb's */
532 /* From the 603e User Manual: "The 603e provides the ability to */
533 /* invalidate a TLB entry. The TLB Invalidate Entry (tlbie) */
534 /* instruction invalidates the TLB entry indexed by the EA, and */
535 /* operates on both the instruction and data TLBs simultaneously*/
536 /* invalidating four TLB entries (both sets in each TLB). The */
537 /* index corresponds to bits 15-19 of the EA. To invalidate all */
538 /* entries within both TLBs, 32 tlbie instructions should be */
539 /* issued, incrementing this field by one each time." */
541 /* "Note that the tlbia instruction is not implemented on the */
544 /* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 */
545 /* incrementing by 0x1000 each time. The code below is sort of */
546 /* based on code in "flush_tlbs" from arch/powerpc/kernel/head.S */
548 /*--------------------------------------------------------------*/
559 /*--------------------------------------------------------------*/
566 * initialise things related to debugging.
568 * must be called after the global offset table (GOT) is initialised
569 * (GET_GOT) and after cpu_init_f() has executed.
575 lis r3, (CONFIG_SYS_IMMR+IM_REGBASE)@h
577 /* Quick and dirty hack to enable the RAM and copy the */
578 /* vectors so that we can take exceptions. */
579 /*--------------------------------------------------------------*/
580 /* write Memory Refresh Prescaler */
581 li r4, CONFIG_SYS_MPTPR
582 sth r4, IM_MPTPR@l(r3)
583 /* write 60x Refresh Timer */
584 li r4, CONFIG_SYS_PSRT
585 stb r4, IM_PSRT@l(r3)
586 /* init the 60x SDRAM Mode Register */
587 lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_NORM)@h
588 ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_NORM)@l
589 stw r4, IM_PSDMR@l(r3)
590 /* write Precharge All Banks command */
591 lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_PREA)@h
592 ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_PREA)@l
593 stw r4, IM_PSDMR@l(r3)
595 /* write eight CBR Refresh commands */
596 lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_CBRR)@h
597 ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_CBRR)@l
598 stw r4, IM_PSDMR@l(r3)
607 /* write Mode Register Write command */
608 lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_MRW)@h
609 ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_MRW)@l
610 stw r4, IM_PSDMR@l(r3)
612 /* write Normal Operation command and enable Refresh */
613 lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_NORM|PSDMR_RFEN)@h
614 ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_NORM|PSDMR_RFEN)@l
615 stw r4, IM_PSDMR@l(r3)
617 /* RAM should now be operational */
619 #define VEC_WRD_CNT ((_end_of_vectors - _start + EXC_OFF_SYS_RESET) / 4)
623 lwz r3, GOT(_end_of_vectors)
624 rlwinm r4, r3, 0, 18, 31 /* _end_of_vectors & 0x3FFF */
625 lis r5, VEC_WRD_CNT@h
626 ori r5, r5, VEC_WRD_CNT@l
633 /* Load the Instruction Address Breakpoint Register (IABR). */
635 /* The address to load is stored in the first word of dual port */
636 /* ram and should be preserved while the power is on, so you */
637 /* can plug addresses into that location then reset the cpu and */
638 /* this code will load that address into the IABR after the */
641 /* When the program counter matches the contents of the IABR, */
642 /* an exception is generated (before the instruction at that */
643 /* location completes). The vector for this exception is 0x1300 */
644 /*--------------------------------------------------------------*/
645 lis r3, CONFIG_SYS_IMMR@h
649 /* Set the entire dual port RAM (where the initial stack */
650 /* resides) to a known value - makes it easier to see where */
651 /* the stack has been written */
652 /*--------------------------------------------------------------*/
653 lis r3, (CONFIG_SYS_IMMR + CONFIG_SYS_INIT_SP_OFFSET)@h
654 ori r3, r3, (CONFIG_SYS_IMMR + CONFIG_SYS_INIT_SP_OFFSET)@l
655 li r4, ((CONFIG_SYS_INIT_SP_OFFSET - 4) / 4)
658 ori r4, r4, 0xdeadbeaf@l
664 /*--------------------------------------------------------------*/
671 * Note: requires that all cache bits in
672 * HID0 are in the low half word.
679 ori r4, r4, HID0_ILOCK
681 ori r4, r3, HID0_ICFI
683 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
685 mtspr HID0, r3 /* clears invalidate */
688 .globl icache_disable
692 ori r4, r4, HID0_ICE|HID0_ILOCK
694 ori r4, r3, HID0_ICFI
696 mtspr HID0, r4 /* sets invalidate, clears enable and lock */
698 mtspr HID0, r3 /* clears invalidate */
704 rlwinm r3, r3, HID0_ICE_BITPOS + 1, 31, 31
712 ori r4, r4, HID0_DLOCK
716 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
718 mtspr HID0, r3 /* clears invalidate */
721 .globl dcache_disable
725 ori r4, r4, HID0_DCE|HID0_DLOCK
729 mtspr HID0, r4 /* sets invalidate, clears enable and lock */
731 mtspr HID0, r3 /* clears invalidate */
737 rlwinm r3, r3, HID0_DCE_BITPOS + 1, 31, 31
745 /*------------------------------------------------------------------------------*/
748 * void relocate_code (addr_sp, gd, addr_moni)
750 * This "function" does not return, instead it continues in RAM
751 * after relocating the monitor code.
755 * r5 = length in bytes
760 mr r1, r3 /* Set new stack pointer */
761 mr r9, r4 /* Save copy of Global Data pointer */
762 mr r10, r5 /* Save copy of Destination Address */
765 mr r3, r5 /* Destination Address */
766 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
767 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
768 lwz r5, GOT(__init_end)
770 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
775 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
781 /* First our own GOT */
783 /* then the one used by the C code */
793 beq cr1,4f /* In place copy is not necessary */
794 beq 7f /* Protect against 0 count */
813 * Now flush the cache: note that we must start from a cache aligned
814 * address. Otherwise we might miss one cache line.
818 beq 7f /* Always flush prefetch queue in any case */
821 mfspr r7,HID0 /* don't do dcbst if dcache is disabled */
822 rlwinm r7,r7,HID0_DCE_BITPOS+1,31,31
830 sync /* Wait for all dcbst to complete on bus */
831 9: mfspr r7,HID0 /* don't do icbi if icache is disabled */
832 rlwinm r7,r7,HID0_ICE_BITPOS+1,31,31
840 7: sync /* Wait for all icbi to complete on bus */
844 * We are done. Do not return, instead branch to second part of board
845 * initialization, now running from RAM.
848 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
855 * Relocation Function, r12 point to got2+0x8000
857 * Adjust got2 pointers, no need to check for 0, this code
858 * already puts a few entries in the table.
860 li r0,__got2_entries@sectoff@l
861 la r3,GOT(_GOT2_TABLE_)
862 lwz r11,GOT(_GOT2_TABLE_)
874 * Now adjust the fixups and the pointers to the fixups
875 * in case we need to move ourselves again.
877 li r0,__fixup_entries@sectoff@l
878 lwz r3,GOT(_FIXUP_TABLE_)
894 * Now clear BSS segment
896 lwz r3,GOT(__bss_start)
897 #if defined(CONFIG_HYMOD)
899 * For HYMOD - the environment is the very last item in flash.
900 * The real .bss stops just before environment starts, so only
901 * clear up to that point.
903 * taken from mods for FADS board
905 lwz r4,GOT(environment)
907 lwz r4,GOT(__bss_end)
921 mr r3, r9 /* Global Data pointer */
922 mr r4, r10 /* Destination Address */
926 * Copy exception vector code to low memory
929 * r7: source address, r8: end address, r9: target address
933 mflr r4 /* save link register */
936 lwz r8, GOT(_end_of_vectors)
938 li r9, 0x100 /* reset vector always at 0x100 */
941 bgelr /* return if r7>=r8 - just in case */
951 * relocate `hdlr' and `int_return' entries
953 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
954 li r8, Alignment - _start + EXC_OFF_SYS_RESET
957 addi r7, r7, 0x100 /* next exception vector */
961 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
964 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
967 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
968 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
971 addi r7, r7, 0x100 /* next exception vector */
975 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
976 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
979 addi r7, r7, 0x100 /* next exception vector */
983 mfmsr r3 /* now that the vectors have */
984 lis r7, MSR_IP@h /* relocated into low memory */
985 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
986 andc r3, r3, r7 /* (if it was on) */
987 SYNC /* Some chip revs need this... */
991 mtlr r4 /* restore link register */