2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * U-Boot - Startup Code for MPC8260 PowerPC based Embedded Boards
30 #include <timestamp.h>
33 #define CONFIG_8260 1 /* needed for Linux kernel header files */
34 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
36 #include <ppc_asm.tmpl>
39 #include <asm/cache.h>
42 #ifndef CONFIG_IDENT_STRING
43 #define CONFIG_IDENT_STRING ""
46 /* We don't want the MMU yet.
49 /* Floating Point enable, Machine Check and Recoverable Interr. */
51 #define MSR_KERNEL (MSR_FP|MSR_RI)
53 #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
57 * Set up GOT: Global Offset Table
59 * Use r12 to access the GOT
62 GOT_ENTRY(_GOT2_TABLE_)
63 GOT_ENTRY(_FIXUP_TABLE_)
66 GOT_ENTRY(_start_of_vectors)
67 GOT_ENTRY(_end_of_vectors)
68 GOT_ENTRY(transfer_to_handler)
72 GOT_ENTRY(__bss_start)
73 #if defined(CONFIG_HYMOD)
74 GOT_ENTRY(environment)
79 * Version string - must be in data segment because MPC8260 uses the first
80 * 256 bytes for the Hard Reset Configuration Word table (see below).
81 * Similarly, can't have the U-Boot Magic Number as the first thing in
82 * the image - don't know how this will affect the image tools, but I guess
89 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
90 .ascii CONFIG_IDENT_STRING, "\0"
93 * Hard Reset Configuration Word (HRCW) table
95 * The Hard Reset Configuration Word (HRCW) sets a number of useful things
96 * such as whether there is an external memory controller, whether the
97 * PowerPC core is disabled (i.e. only the communications processor is
98 * active, accessed by another CPU on the bus), whether using external
99 * arbitration, external bus mode, boot port size, core initial prefix,
100 * internal space base, boot memory space, etc.
102 * These things dictate where the processor begins execution, where the
103 * boot ROM appears in memory, the memory controller setup when access
104 * boot ROM, etc. The HRCW is *extremely* important.
106 * The HRCW is read from the bus during reset. One CPU on the bus will
107 * be a hard reset configuration master, any others will be hard reset
108 * configuration slaves. The master reads eight HRCWs from flash during
109 * reset - the first it uses for itself, the other 7 it communicates to
110 * up to 7 configuration slaves by some complicated mechanism, which is
111 * not really important here.
113 * The configuration master performs 32 successive reads starting at address
114 * 0 and incrementing by 8 each read (i.e. on 64 bit boundaries) but only 8
115 * bits is read, and always from byte lane D[0-7] (so that port size of the
116 * boot device does not matter). The first four reads form the 32 bit HRCW
117 * for the master itself. The second four reads form the HRCW for the first
118 * slave, and so on, up to seven slaves. The 32 bit HRCW is formed by
119 * concatenating the four bytes, with the first read placed in byte 0 (the
120 * most significant byte), and so on with the fourth read placed in byte 3
121 * (the least significant byte).
123 #define _HRCW_TABLE_ENTRY(w) \
124 .fill 8,1,(((w)>>24)&0xff); \
125 .fill 8,1,(((w)>>16)&0xff); \
126 .fill 8,1,(((w)>> 8)&0xff); \
127 .fill 8,1,(((w) )&0xff)
131 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_MASTER)
132 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE1)
133 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE2)
134 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE3)
135 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE4)
136 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE5)
137 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE6)
138 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE7)
140 * After configuration, a system reset exception is executed using the
141 * vector at offset 0x100 relative to the base set by MSR[IP]. If MSR[IP]
142 * is 0, the base address is 0x00000000. If MSR[IP] is 1, the base address
143 * is 0xfff00000. In the case of a Power On Reset or Hard Reset, the value
144 * of MSR[IP] is determined by the CIP field in the HRCW.
146 * Other bits in the HRCW set up the Base Address and Port Size in BR0.
147 * This determines the location of the boot ROM (flash or EPROM) in the
148 * processor's address space at boot time. As long as the HRCW is set up
149 * so that we eventually end up executing the code below when the processor
150 * executes the reset exception, the actual values used should not matter.
152 * Once we have got here, the address mask in OR0 is cleared so that the
153 * bottom 32K of the boot ROM is effectively repeated all throughout the
154 * processor's address space, after which we can jump to the absolute
155 * address at which the boot ROM was linked at compile time, and proceed
156 * to initialise the memory controller without worrying if the rug will be
157 * pulled out from under us, so to speak (it will be fine as long as we
158 * configure BR0 with the same boot ROM link address).
160 . = EXC_OFF_SYS_RESET
164 #if defined(CONFIG_MPC8260ADS) && defined(CONFIG_SYS_DEFAULT_IMMR)
165 lis r3, CONFIG_SYS_DEFAULT_IMMR@h
169 rlwinm r4, r4, 0, 8, 5
175 #endif /* CONFIG_MPC8260ADS && CONFIG_SYS_DEFAULT_IMMR */
177 mfmsr r5 /* save msr contents */
179 #if defined(CONFIG_COGENT)
180 /* this is what the cogent EPROM does */
185 #endif /* CONFIG_COGENT */
187 #if defined(CONFIG_SYS_DEFAULT_IMMR)
188 lis r3, CONFIG_SYS_IMMR@h
189 ori r3, r3, CONFIG_SYS_IMMR@l
190 lis r4, CONFIG_SYS_DEFAULT_IMMR@h
192 #endif /* CONFIG_SYS_DEFAULT_IMMR */
194 /* Initialise the MPC8260 processor core */
195 /*--------------------------------------------------------------*/
199 #ifndef CONFIG_SYS_RAMBOOT
200 /* When booting from ROM (Flash or EPROM), clear the */
201 /* Address Mask in OR0 so ROM appears everywhere */
202 /*--------------------------------------------------------------*/
204 lis r3, (CONFIG_SYS_IMMR+IM_REGBASE)@h
210 /* Calculate absolute address in FLASH and jump there */
211 /*--------------------------------------------------------------*/
213 lis r3, CONFIG_SYS_MONITOR_BASE@h
214 ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
215 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
220 #endif /* CONFIG_SYS_RAMBOOT */
222 /* initialize some things that are hard to access from C */
223 /*--------------------------------------------------------------*/
225 lis r3, CONFIG_SYS_IMMR@h /* set up stack in internal DPRAM */
226 ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET
227 li r0, 0 /* Make room for stack frame header and */
228 stwu r0, -4(r1) /* clear final stack frame so that */
229 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
231 /* let the C-code set up the rest */
233 /* Be careful to keep code relocatable ! */
234 /*--------------------------------------------------------------*/
236 GET_GOT /* initialize GOT access */
239 bl cpu_init_f /* run low-level CPU init code (in Flash)*/
242 bl init_debug /* set up debugging stuff */
245 bl board_init_f /* run 1st part of board init code (in Flash)*/
247 /* NOTREACHED - board_init_f() does not return */
253 .globl _start_of_vectors
257 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
259 /* Data Storage exception. */
260 STD_EXCEPTION(0x300, DataStorage, UnknownException)
262 /* Instruction Storage exception. */
263 STD_EXCEPTION(0x400, InstStorage, UnknownException)
265 /* External Interrupt exception. */
266 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
268 /* Alignment exception. */
271 EXCEPTION_PROLOG(SRR0, SRR1)
276 addi r3,r1,STACK_FRAME_OVERHEAD
277 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
279 /* Program check exception */
282 EXCEPTION_PROLOG(SRR0, SRR1)
283 addi r3,r1,STACK_FRAME_OVERHEAD
284 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
287 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
289 /* I guess we could implement decrementer, and may have
290 * to someday for timekeeping.
292 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
294 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
295 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
296 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
297 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
299 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
300 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
302 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
303 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
304 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
308 * This exception occurs when the program counter matches the
309 * Instruction Address Breakpoint Register (IABR).
311 * I want the cpu to halt if this occurs so I can hunt around
312 * with the debugger and look at things.
314 * When DEBUG is defined, both machine check enable (in the MSR)
315 * and checkstop reset enable (in the reset mode register) are
316 * turned off and so a checkstop condition will result in the cpu
319 * I force the cpu into a checkstop condition by putting an illegal
320 * instruction here (at least this is the theory).
322 * well - that didnt work, so just do an infinite loop!
326 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
328 STD_EXCEPTION(0x1400, SMI, UnknownException)
330 STD_EXCEPTION(0x1500, Trap_15, UnknownException)
331 STD_EXCEPTION(0x1600, Trap_16, UnknownException)
332 STD_EXCEPTION(0x1700, Trap_17, UnknownException)
333 STD_EXCEPTION(0x1800, Trap_18, UnknownException)
334 STD_EXCEPTION(0x1900, Trap_19, UnknownException)
335 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
336 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
337 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
338 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
339 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
340 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
341 STD_EXCEPTION(0x2000, Trap_20, UnknownException)
342 STD_EXCEPTION(0x2100, Trap_21, UnknownException)
343 STD_EXCEPTION(0x2200, Trap_22, UnknownException)
344 STD_EXCEPTION(0x2300, Trap_23, UnknownException)
345 STD_EXCEPTION(0x2400, Trap_24, UnknownException)
346 STD_EXCEPTION(0x2500, Trap_25, UnknownException)
347 STD_EXCEPTION(0x2600, Trap_26, UnknownException)
348 STD_EXCEPTION(0x2700, Trap_27, UnknownException)
349 STD_EXCEPTION(0x2800, Trap_28, UnknownException)
350 STD_EXCEPTION(0x2900, Trap_29, UnknownException)
351 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
352 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
353 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
354 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
355 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
356 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
359 .globl _end_of_vectors
365 * This code finishes saving the registers to the exception frame
366 * and jumps to the appropriate handler for the exception.
367 * Register r21 is pointer into trap frame, r1 has new stack pointer.
369 .globl transfer_to_handler
380 andi. r24,r23,0x3f00 /* get vector offset */
384 lwz r24,0(r23) /* virtual address of handler */
385 lwz r23,4(r23) /* where to go when done */
390 rfi /* jump to handler, enable MMU */
393 mfmsr r28 /* Disable interrupts */
397 SYNC /* Some chip revs need this... */
412 lwz r2,_NIP(r1) /* Restore environment */
422 #if defined(CONFIG_COGENT)
425 * This code initialises the MPC8260 processor core
426 * (conforms to PowerPC 603e spec)
429 .globl cogent_init_8260
432 /* Taken from page 14 of CMA282 manual */
433 /*--------------------------------------------------------------*/
435 lis r4, (CONFIG_SYS_IMMR+IM_REGBASE)@h
436 lis r3, CONFIG_SYS_IMMR@h
437 stw r3, IM_IMMR@l(r4)
438 lwz r3, IM_IMMR@l(r4)
440 lis r3, CONFIG_SYS_SYPCR@h
441 ori r3, r3, CONFIG_SYS_SYPCR@l
442 stw r3, IM_SYPCR@l(r4)
443 lwz r3, IM_SYPCR@l(r4)
445 lis r3, CONFIG_SYS_SCCR@h
446 ori r3, r3, CONFIG_SYS_SCCR@l
447 stw r3, IM_SCCR@l(r4)
448 lwz r3, IM_SCCR@l(r4)
451 /* the rest of this was disassembled from the */
452 /* EPROM code that came with my CMA282 CPU module */
453 /*--------------------------------------------------------------*/
467 /*--------------------------------------------------------------*/
471 #endif /* CONFIG_COGENT */
474 * This code initialises the MPC8260 processor core
475 * (conforms to PowerPC 603e spec)
476 * Note: expects original MSR contents to be in r5.
479 .globl init_8260_core
482 /* Initialize machine status; enable machine check interrupt */
483 /*--------------------------------------------------------------*/
485 li r3, MSR_KERNEL /* Set ME and RI flags */
486 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */
488 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
490 SYNC /* Some chip revs need this... */
493 mtspr SRR1, r3 /* Make SRR1 match MSR */
495 /* Initialise the SYPCR early, and reset the watchdog (if req) */
496 /*--------------------------------------------------------------*/
498 lis r3, (CONFIG_SYS_IMMR+IM_REGBASE)@h
499 #if !defined(CONFIG_COGENT)
500 lis r4, CONFIG_SYS_SYPCR@h
501 ori r4, r4, CONFIG_SYS_SYPCR@l
502 stw r4, IM_SYPCR@l(r3)
503 #endif /* !CONFIG_COGENT */
504 #if defined(CONFIG_WATCHDOG)
505 li r4, 21868 /* = 0x556c */
506 sth r4, IM_SWSR@l(r3)
507 li r4, -21959 /* = 0xaa39 */
508 sth r4, IM_SWSR@l(r3)
509 #endif /* CONFIG_WATCHDOG */
511 /* Initialize the Hardware Implementation-dependent Registers */
512 /* HID0 also contains cache control */
513 /*--------------------------------------------------------------*/
515 lis r3, CONFIG_SYS_HID0_INIT@h
516 ori r3, r3, CONFIG_SYS_HID0_INIT@l
520 lis r3, CONFIG_SYS_HID0_FINAL@h
521 ori r3, r3, CONFIG_SYS_HID0_FINAL@l
525 lis r3, CONFIG_SYS_HID2@h
526 ori r3, r3, CONFIG_SYS_HID2@l
529 /* clear all BAT's */
530 /*--------------------------------------------------------------*/
551 /* invalidate all tlb's */
553 /* From the 603e User Manual: "The 603e provides the ability to */
554 /* invalidate a TLB entry. The TLB Invalidate Entry (tlbie) */
555 /* instruction invalidates the TLB entry indexed by the EA, and */
556 /* operates on both the instruction and data TLBs simultaneously*/
557 /* invalidating four TLB entries (both sets in each TLB). The */
558 /* index corresponds to bits 15-19 of the EA. To invalidate all */
559 /* entries within both TLBs, 32 tlbie instructions should be */
560 /* issued, incrementing this field by one each time." */
562 /* "Note that the tlbia instruction is not implemented on the */
565 /* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 */
566 /* incrementing by 0x1000 each time. The code below is sort of */
567 /* based on code in "flush_tlbs" from arch/powerpc/kernel/head.S */
569 /*--------------------------------------------------------------*/
580 /*--------------------------------------------------------------*/
587 * initialise things related to debugging.
589 * must be called after the global offset table (GOT) is initialised
590 * (GET_GOT) and after cpu_init_f() has executed.
596 lis r3, (CONFIG_SYS_IMMR+IM_REGBASE)@h
598 /* Quick and dirty hack to enable the RAM and copy the */
599 /* vectors so that we can take exceptions. */
600 /*--------------------------------------------------------------*/
601 /* write Memory Refresh Prescaler */
602 li r4, CONFIG_SYS_MPTPR
603 sth r4, IM_MPTPR@l(r3)
604 /* write 60x Refresh Timer */
605 li r4, CONFIG_SYS_PSRT
606 stb r4, IM_PSRT@l(r3)
607 /* init the 60x SDRAM Mode Register */
608 lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_NORM)@h
609 ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_NORM)@l
610 stw r4, IM_PSDMR@l(r3)
611 /* write Precharge All Banks command */
612 lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_PREA)@h
613 ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_PREA)@l
614 stw r4, IM_PSDMR@l(r3)
616 /* write eight CBR Refresh commands */
617 lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_CBRR)@h
618 ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_CBRR)@l
619 stw r4, IM_PSDMR@l(r3)
628 /* write Mode Register Write command */
629 lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_MRW)@h
630 ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_MRW)@l
631 stw r4, IM_PSDMR@l(r3)
633 /* write Normal Operation command and enable Refresh */
634 lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_NORM|PSDMR_RFEN)@h
635 ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_NORM|PSDMR_RFEN)@l
636 stw r4, IM_PSDMR@l(r3)
638 /* RAM should now be operational */
640 #define VEC_WRD_CNT ((_end_of_vectors - _start + EXC_OFF_SYS_RESET) / 4)
644 lwz r3, GOT(_end_of_vectors)
645 rlwinm r4, r3, 0, 18, 31 /* _end_of_vectors & 0x3FFF */
646 lis r5, VEC_WRD_CNT@h
647 ori r5, r5, VEC_WRD_CNT@l
654 /* Load the Instruction Address Breakpoint Register (IABR). */
656 /* The address to load is stored in the first word of dual port */
657 /* ram and should be preserved while the power is on, so you */
658 /* can plug addresses into that location then reset the cpu and */
659 /* this code will load that address into the IABR after the */
662 /* When the program counter matches the contents of the IABR, */
663 /* an exception is generated (before the instruction at that */
664 /* location completes). The vector for this exception is 0x1300 */
665 /*--------------------------------------------------------------*/
666 lis r3, CONFIG_SYS_IMMR@h
670 /* Set the entire dual port RAM (where the initial stack */
671 /* resides) to a known value - makes it easier to see where */
672 /* the stack has been written */
673 /*--------------------------------------------------------------*/
674 lis r3, (CONFIG_SYS_IMMR + CONFIG_SYS_INIT_SP_OFFSET)@h
675 ori r3, r3, (CONFIG_SYS_IMMR + CONFIG_SYS_INIT_SP_OFFSET)@l
676 li r4, ((CONFIG_SYS_INIT_SP_OFFSET - 4) / 4)
679 ori r4, r4, 0xdeadbeaf@l
685 /*--------------------------------------------------------------*/
692 * Note: requires that all cache bits in
693 * HID0 are in the low half word.
700 ori r4, r4, HID0_ILOCK
702 ori r4, r3, HID0_ICFI
704 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
706 mtspr HID0, r3 /* clears invalidate */
709 .globl icache_disable
713 ori r4, r4, HID0_ICE|HID0_ILOCK
715 ori r4, r3, HID0_ICFI
717 mtspr HID0, r4 /* sets invalidate, clears enable and lock */
719 mtspr HID0, r3 /* clears invalidate */
725 rlwinm r3, r3, HID0_ICE_BITPOS + 1, 31, 31
733 ori r4, r4, HID0_DLOCK
737 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
739 mtspr HID0, r3 /* clears invalidate */
742 .globl dcache_disable
746 ori r4, r4, HID0_DCE|HID0_DLOCK
750 mtspr HID0, r4 /* sets invalidate, clears enable and lock */
752 mtspr HID0, r3 /* clears invalidate */
758 rlwinm r3, r3, HID0_DCE_BITPOS + 1, 31, 31
766 /*------------------------------------------------------------------------------*/
769 * void relocate_code (addr_sp, gd, addr_moni)
771 * This "function" does not return, instead it continues in RAM
772 * after relocating the monitor code.
776 * r5 = length in bytes
781 mr r1, r3 /* Set new stack pointer */
782 mr r9, r4 /* Save copy of Global Data pointer */
783 mr r10, r5 /* Save copy of Destination Address */
786 mr r3, r5 /* Destination Address */
787 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
788 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
789 lwz r5, GOT(__init_end)
791 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
796 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
802 /* First our own GOT */
804 /* then the one used by the C code */
814 beq cr1,4f /* In place copy is not necessary */
815 beq 7f /* Protect against 0 count */
834 * Now flush the cache: note that we must start from a cache aligned
835 * address. Otherwise we might miss one cache line.
839 beq 7f /* Always flush prefetch queue in any case */
842 mfspr r7,HID0 /* don't do dcbst if dcache is disabled */
843 rlwinm r7,r7,HID0_DCE_BITPOS+1,31,31
851 sync /* Wait for all dcbst to complete on bus */
852 9: mfspr r7,HID0 /* don't do icbi if icache is disabled */
853 rlwinm r7,r7,HID0_ICE_BITPOS+1,31,31
861 7: sync /* Wait for all icbi to complete on bus */
865 * We are done. Do not return, instead branch to second part of board
866 * initialization, now running from RAM.
869 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
876 * Relocation Function, r12 point to got2+0x8000
878 * Adjust got2 pointers, no need to check for 0, this code
879 * already puts a few entries in the table.
881 li r0,__got2_entries@sectoff@l
882 la r3,GOT(_GOT2_TABLE_)
883 lwz r11,GOT(_GOT2_TABLE_)
895 * Now adjust the fixups and the pointers to the fixups
896 * in case we need to move ourselves again.
898 li r0,__fixup_entries@sectoff@l
899 lwz r3,GOT(_FIXUP_TABLE_)
913 * Now clear BSS segment
915 lwz r3,GOT(__bss_start)
916 #if defined(CONFIG_HYMOD)
918 * For HYMOD - the environment is the very last item in flash.
919 * The real .bss stops just before environment starts, so only
920 * clear up to that point.
922 * taken from mods for FADS board
924 lwz r4,GOT(environment)
940 mr r3, r9 /* Global Data pointer */
941 mr r4, r10 /* Destination Address */
945 * Copy exception vector code to low memory
948 * r7: source address, r8: end address, r9: target address
952 mflr r4 /* save link register */
955 lwz r8, GOT(_end_of_vectors)
957 li r9, 0x100 /* reset vector always at 0x100 */
960 bgelr /* return if r7>=r8 - just in case */
970 * relocate `hdlr' and `int_return' entries
972 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
973 li r8, Alignment - _start + EXC_OFF_SYS_RESET
976 addi r7, r7, 0x100 /* next exception vector */
980 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
983 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
986 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
987 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
990 addi r7, r7, 0x100 /* next exception vector */
994 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
995 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
998 addi r7, r7, 0x100 /* next exception vector */
1002 mfmsr r3 /* now that the vectors have */
1003 lis r7, MSR_IP@h /* relocated into low memory */
1004 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
1005 andc r3, r3, r7 /* (if it was on) */
1006 SYNC /* Some chip revs need this... */
1010 mtlr r4 /* restore link register */