2 * Copyright 2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm/fsl_serdes.h>
9 #include <asm/immap_85xx.h>
11 #include <asm/processor.h>
12 #include <asm/fsl_law.h>
13 #include <linux/errno.h>
14 #include <fsl_errata.h>
15 #include "fsl_corenet2_serdes.h"
17 #ifdef CONFIG_SYS_FSL_SRDS_1
18 static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
20 #ifdef CONFIG_SYS_FSL_SRDS_2
21 static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
23 #ifdef CONFIG_SYS_FSL_SRDS_3
24 static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT];
26 #ifdef CONFIG_SYS_FSL_SRDS_4
27 static u8 serdes4_prtcl_map[SERDES_PRCTL_COUNT];
31 static const char *serdes_prtcl_str[] = {
41 [SGMII_FM1_DTSEC1] = "SGMII_FM1_DTSEC1",
42 [SGMII_FM1_DTSEC2] = "SGMII_FM1_DTSEC2",
43 [SGMII_FM1_DTSEC3] = "SGMII_FM1_DTSEC3",
44 [SGMII_FM1_DTSEC4] = "SGMII_FM1_DTSEC4",
45 [SGMII_FM1_DTSEC5] = "SGMII_FM1_DTSEC5",
46 [SGMII_FM1_DTSEC6] = "SGMII_FM1_DTSEC6",
47 [SGMII_FM2_DTSEC1] = "SGMII_FM2_DTSEC1",
48 [SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2",
49 [SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3",
50 [SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4",
51 [XAUI_FM1] = "XAUI_FM1",
52 [XAUI_FM2] = "XAUI_FM2",
62 [XAUI_FM1_MAC9] = "XAUI_FM1_MAC9",
63 [XAUI_FM1_MAC10] = "XAUI_FM1_MAC10",
64 [XAUI_FM2_MAC9] = "XAUI_FM2_MAC9",
65 [XAUI_FM2_MAC10] = "XAUI_FM2_MAC10",
66 [HIGIG_FM1_MAC9] = "HiGig_FM1_MAC9",
67 [HIGIG_FM1_MAC10] = "HiGig_FM1_MAC10",
68 [HIGIG_FM2_MAC9] = "HiGig_FM2_MAC9",
69 [HIGIG_FM2_MAC10] = "HiGig_FM2_MAC10",
70 [QSGMII_FM1_A] = "QSGMII_FM1_A",
71 [QSGMII_FM1_B] = "QSGMII_FM1_B",
72 [QSGMII_FM2_A] = "QSGMII_FM2_A",
73 [QSGMII_FM2_B] = "QSGMII_FM2_B",
74 [XFI_FM1_MAC9] = "XFI_FM1_MAC9",
75 [XFI_FM1_MAC10] = "XFI_FM1_MAC10",
76 [XFI_FM2_MAC9] = "XFI_FM2_MAC9",
77 [XFI_FM2_MAC10] = "XFI_FM2_MAC10",
78 [INTERLAKEN] = "INTERLAKEN",
79 [QSGMII_SW1_A] = "QSGMII_SW1_A",
80 [QSGMII_SW1_B] = "QSGMII_SW1_B",
81 [SGMII_SW1_MAC1] = "SGMII_SW1_MAC1",
82 [SGMII_SW1_MAC2] = "SGMII_SW1_MAC2",
83 [SGMII_SW1_MAC3] = "SGMII_SW1_MAC3",
84 [SGMII_SW1_MAC4] = "SGMII_SW1_MAC4",
85 [SGMII_SW1_MAC5] = "SGMII_SW1_MAC5",
86 [SGMII_SW1_MAC6] = "SGMII_SW1_MAC6",
90 int is_serdes_configured(enum srds_prtcl device)
94 #ifdef CONFIG_SYS_FSL_SRDS_1
95 if (!serdes1_prtcl_map[NONE])
98 ret |= serdes1_prtcl_map[device];
100 #ifdef CONFIG_SYS_FSL_SRDS_2
101 if (!serdes2_prtcl_map[NONE])
104 ret |= serdes2_prtcl_map[device];
106 #ifdef CONFIG_SYS_FSL_SRDS_3
107 if (!serdes3_prtcl_map[NONE])
110 ret |= serdes3_prtcl_map[device];
112 #ifdef CONFIG_SYS_FSL_SRDS_4
113 if (!serdes4_prtcl_map[NONE])
116 ret |= serdes4_prtcl_map[device];
122 int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
124 const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
125 u32 cfg = in_be32(&gur->rcwsr[4]);
129 #ifdef CONFIG_SYS_FSL_SRDS_1
131 cfg &= FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
132 cfg >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
135 #ifdef CONFIG_SYS_FSL_SRDS_2
137 cfg &= FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
138 cfg >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
141 #ifdef CONFIG_SYS_FSL_SRDS_3
143 cfg &= FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
144 cfg >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
147 #ifdef CONFIG_SYS_FSL_SRDS_4
149 cfg &= FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
150 cfg >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
154 printf("invalid SerDes%d\n", sd);
157 /* Is serdes enabled at all? */
158 if (unlikely(cfg == 0))
161 for (i = 0; i < SRDS_MAX_LANES; i++) {
162 if (serdes_get_prtcl(sd, cfg, i) == device)
182 #define FUSE_VAL_MASK 0x00000003
183 #define FUSE_VAL_SHIFT 30
184 #define CR0_DCBIAS_SHIFT 5
185 #define CR1_FCAP_SHIFT 15
186 #define CR1_BCAP_SHIFT 29
187 #define FCAP_MASK 0x001F8000
188 #define BCAP_MASK 0x20000000
189 #define BCAP_OVD_MASK 0x10000000
190 #define BYP_CAL_MASK 0x02000000
192 void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
193 u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
195 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
199 if (serdes_prtcl_map[NONE])
202 memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
203 #ifdef CONFIG_SYS_FSL_ERRATUM_A007186
204 struct ccsr_sfp_regs __iomem *sfp_regs =
205 (struct ccsr_sfp_regs __iomem *)(CONFIG_SYS_SFP_ADDR);
206 u32 pll_num, pll_status, bc, dc, fc, pll_cr_upd, pll_cr0, pll_cr1;
207 u32 bc_status, fc_status, dc_status, pll_sr2;
208 serdes_corenet_t __iomem *srds_regs = (void *)sd_addr;
212 cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask;
215 * Freescale Scratch Pad Fuse Register n (SFP_FSPFR0)
216 * The workaround requires factory pre-set SerDes calibration values to be
217 * read from a fuse block(Freescale Scratch Pad Fuse Register SFP_FSPFR0)
218 * These values have been shown to work across the
219 * entire temperature range for all SerDes. These values are then written into
220 * the SerDes registers to calibrate the SerDes PLL.
222 * This workaround for the protocols and rates that only have the Ring VCO.
224 #ifdef CONFIG_SYS_FSL_ERRATUM_A007186
225 sfp_spfr0 = in_be32(&sfp_regs->fsl_spfr0);
226 debug("A007186: sfp_spfr0= %x\n", sfp_spfr0);
228 sel = (sfp_spfr0 >> FUSE_VAL_SHIFT) & FUSE_VAL_MASK;
230 if (has_erratum_a007186() && (sel == 0x01 || sel == 0x02)) {
231 for (pll_num = 0; pll_num < SRDS_MAX_BANK; pll_num++) {
232 pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0);
233 debug("A007186: pll_num=%x pllcr0=%x\n",
234 pll_num, pll_status);
236 /* Read factory pre-set SerDes calibration values
237 * from fuse block(SFP scratch register-sfp_spfr0)
239 switch (pll_status & SRDS_PLLCR0_FRATE_SEL_MASK) {
240 case SRDS_PLLCR0_FRATE_SEL_3_0:
241 case SRDS_PLLCR0_FRATE_SEL_3_072:
242 debug("A007186: 3.0/3.072 protocol rate\n");
243 bc = (sfp_spfr0 >> BC1_SHIFT) & BC_MASK;
244 dc = (sfp_spfr0 >> DC1_SHIFT) & DC_MASK;
245 fc = (sfp_spfr0 >> FC1_SHIFT) & FC_MASK;
247 case SRDS_PLLCR0_FRATE_SEL_3_125:
248 debug("A007186: 3.125 protocol rate\n");
249 bc = (sfp_spfr0 >> BC2_SHIFT) & BC_MASK;
250 dc = (sfp_spfr0 >> DC2_SHIFT) & DC_MASK;
251 fc = (sfp_spfr0 >> FC2_SHIFT) & FC_MASK;
253 case SRDS_PLLCR0_FRATE_SEL_3_75:
254 debug("A007186: 3.75 protocol rate\n");
255 bc = (sfp_spfr0 >> BC1_SHIFT) & BC_MASK;
256 dc = (sfp_spfr0 >> DC1_SHIFT) & DC_MASK;
257 fc = (sfp_spfr0 >> FC1_SHIFT) & FC_MASK;
264 /* Write SRDSxPLLnCR1[11:16] = FC
265 * Write SRDSxPLLnCR1[2] = BC
267 pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1);
268 pll_cr_upd = (((bc << CR1_BCAP_SHIFT) & BCAP_MASK) |
269 ((fc << CR1_FCAP_SHIFT) & FCAP_MASK));
270 out_be32(&srds_regs->bank[pll_num].pllcr1,
271 (pll_cr_upd | pll_cr1));
272 debug("A007186: pll_num=%x Updated PLLCR1=%x\n",
273 pll_num, (pll_cr_upd | pll_cr1));
274 /* Write SRDSxPLLnCR0[24:26] = DC
276 pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
277 out_be32(&srds_regs->bank[pll_num].pllcr0,
278 pll_cr0 | (dc << CR0_DCBIAS_SHIFT));
279 debug("A007186: pll_num=%x, Updated PLLCR0=%x\n",
280 pll_num, (pll_cr0 | (dc << CR0_DCBIAS_SHIFT)));
281 /* Write SRDSxPLLnCR1[3] = 1
282 * Write SRDSxPLLnCR1[6] = 1
284 pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1);
285 pll_cr_upd = (BCAP_OVD_MASK | BYP_CAL_MASK);
286 out_be32(&srds_regs->bank[pll_num].pllcr1,
287 (pll_cr_upd | pll_cr1));
288 debug("A007186: pll_num=%x Updated PLLCR1=%x\n",
289 pll_num, (pll_cr_upd | pll_cr1));
292 /* Read the status Registers */
293 /* Verify SRDSxPLLnSR2[8] = BC */
294 pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2);
295 debug("A007186: pll_num=%x pllsr2=%x\n",
297 bc_status = (pll_sr2 >> 23) & BC_MASK;
299 debug("BC mismatch\n");
300 fc_status = (pll_sr2 >> 16) & FC_MASK;
302 debug("FC mismatch\n");
303 pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
304 out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 |
306 pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2);
307 dc_status = (pll_sr2 >> 17) & DC_MASK;
309 debug("DC mismatch\n");
310 pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
311 out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 &
315 /* Wait 750us to verify the PLL is locked
316 * by checking SRDSxPLLnCR0[8] = 1.
319 pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0);
320 debug("A007186: pll_num=%x pllcr0=%x\n",
321 pll_num, pll_status);
323 if ((pll_status & SRDS_PLLCR0_PLL_LCK) == 0)
324 printf("A007186 Serdes PLL not locked\n");
326 debug("A007186 Serdes PLL locked\n");
331 cfg >>= sd_prctl_shift;
332 printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
333 if (!is_serdes_prtcl_valid(sd, cfg))
334 printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
336 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
337 enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
338 if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
339 debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
341 serdes_prtcl_map[lane_prtcl] = 1;
344 /* Set the first element to indicate serdes has been initialized */
345 serdes_prtcl_map[NONE] = 1;
348 void fsl_serdes_init(void)
351 #ifdef CONFIG_SYS_FSL_SRDS_1
352 serdes_init(FSL_SRDS_1,
353 CONFIG_SYS_FSL_CORENET_SERDES_ADDR,
354 FSL_CORENET2_RCWSR4_SRDS1_PRTCL,
355 FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT,
358 #ifdef CONFIG_SYS_FSL_SRDS_2
359 serdes_init(FSL_SRDS_2,
360 CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
361 FSL_CORENET2_RCWSR4_SRDS2_PRTCL,
362 FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT,
365 #ifdef CONFIG_SYS_FSL_SRDS_3
366 serdes_init(FSL_SRDS_3,
367 CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
368 FSL_CORENET2_RCWSR4_SRDS3_PRTCL,
369 FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT,
372 #ifdef CONFIG_SYS_FSL_SRDS_4
373 serdes_init(FSL_SRDS_4,
374 CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000,
375 FSL_CORENET2_RCWSR4_SRDS4_PRTCL,
376 FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT,
382 const char *serdes_clock_to_string(u32 clock)
385 case SRDS_PLLCR0_RFCK_SEL_100:
387 case SRDS_PLLCR0_RFCK_SEL_125:
389 case SRDS_PLLCR0_RFCK_SEL_156_25:
391 case SRDS_PLLCR0_RFCK_SEL_161_13:
392 return "161.1328123";
394 #if defined(CONFIG_T4240QDS)