2 * Copyright 2004, 2007, 2008 Freescale Semiconductor.
3 * Srikanth Srinivasan <srikanth.srinivaan@freescale.com>
5 * SPDX-License-Identifier: GPL-2.0+
11 #include <ppc_asm.tmpl>
14 #include <asm/cache.h>
17 /* If this is a multi-cpu system then we need to handle the
18 * 2nd cpu. The assumption is that the 2nd cpu is being
19 * held in boot holdoff mode until the 1st cpu unlocks it
20 * from Linux. We'll do some basic cpu init and then pass
21 * it to the Linux Reset Vector.
22 * Sri: Much of this initialization is not required. Linux
23 * rewrites the bats, and the sprs and also enables the L1 cache.
25 * Core 0 must copy this to a 1M aligned region and set BPTR
29 .globl __secondary_start_page
30 __secondary_start_page:
31 .space 0x100 /* space over to reset vector loc */
59 /* enable extended addressing */
61 lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h
62 ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l
68 /* init the L2 cache */
69 addis r3, r0, L2_INIT@h
76 /* invalidate the L2 cache */
78 rlwinm. r3, r3, 0, 0, 0
82 rlwinm r3, r3, 0, 1, 31
91 oris r3, r3, L2CR_L2I@h
96 andis. r3, r3, L2CR_L2I@h
101 /* enable and invalidate the data cache */
103 li r5, HID0_DCFI|HID0_DLOCK
105 mtspr HID0, r3 /* no invalidate, unlock */
107 ori r5, r3, HID0_DCFI
108 mtspr HID0, r5 /* enable + invalidate */
109 mtspr HID0, r3 /* enable */
114 ori r3, r3, L2_ENABLE@l
120 /* enable and invalidate the instruction cache*/
122 li r5, HID0_ICFI|HID0_ILOCK
125 ori r5, r3, HID0_ICFI
138 /* MCP|SYNCBE|ABE in HID1 */
146 lis r3, CONFIG_LINUX_RESET_VEC@h
147 ori r3, r3, CONFIG_LINUX_RESET_VEC@l
151 /* Never Returns, Running in Linux Now */