2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #if defined(CONFIG_SYS_RTCSC) || defined(CONFIG_SYS_RMDS)
31 DECLARE_GLOBAL_DATA_PTR;
34 #if defined(CONFIG_SYS_I2C_UCODE_PATCH) || defined(CONFIG_SYS_SPI_UCODE_PATCH) || \
35 defined(CONFIG_SYS_SMC_UCODE_PATCH)
36 void cpm_load_patch (volatile immap_t * immr);
40 * Breath some life into the CPU...
42 * Set up the memory map,
43 * initialize a bunch of registers,
44 * initialize the UPM's
46 void cpu_init_f (volatile immap_t * immr)
49 volatile memctl8xx_t *memctl = &immr->im_memctl;
50 # ifdef CONFIG_SYS_PLPRCR
56 /* SYPCR - contains watchdog control (11-9) */
58 immr->im_siu_conf.sc_sypcr = CONFIG_SYS_SYPCR;
60 #if defined(CONFIG_WATCHDOG)
61 reset_8xx_watchdog (immr);
62 #endif /* CONFIG_WATCHDOG */
64 /* SIUMCR - contains debug pin configuration (11-6) */
65 #ifndef CONFIG_SVM_SC8xx
66 immr->im_siu_conf.sc_siumcr |= CONFIG_SYS_SIUMCR;
68 immr->im_siu_conf.sc_siumcr = CONFIG_SYS_SIUMCR;
70 /* initialize timebase status and control register (11-26) */
73 immr->im_sitk.sitk_tbscrk = KAPWR_KEY;
74 immr->im_sit.sit_tbscr = CONFIG_SYS_TBSCR;
76 /* initialize the PIT (11-31) */
78 immr->im_sitk.sitk_piscrk = KAPWR_KEY;
79 immr->im_sit.sit_piscr = CONFIG_SYS_PISCR;
81 /* System integration timers. Don't change EBDF! (15-27) */
83 immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
84 reg = immr->im_clkrst.car_sccr;
86 reg |= CONFIG_SYS_SCCR;
87 immr->im_clkrst.car_sccr = reg;
89 /* PLL (CPU clock) settings (15-30) */
91 immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
93 #ifndef CONFIG_MBX /* MBX board does things different */
95 /* If CONFIG_SYS_PLPRCR (set in the various *_config.h files) tries to
96 * set the MF field, then just copy CONFIG_SYS_PLPRCR over car_plprcr,
97 * otherwise OR in CONFIG_SYS_PLPRCR so we do not change the current MF
100 * For newer (starting MPC866) chips PLPRCR layout is different.
102 #ifdef CONFIG_SYS_PLPRCR
103 if (get_immr(0xFFFF) >= MPC8xx_NEW_CLK)
104 mfmask = PLPRCR_MFACT_MSK;
106 mfmask = PLPRCR_MF_MSK;
108 if ((CONFIG_SYS_PLPRCR & mfmask) != 0)
109 reg = CONFIG_SYS_PLPRCR; /* reset control bits */
111 reg = immr->im_clkrst.car_plprcr;
112 reg &= mfmask; /* isolate MF-related fields */
113 reg |= CONFIG_SYS_PLPRCR; /* reset control bits */
115 immr->im_clkrst.car_plprcr = reg;
122 /* perform BR0 reset that MPC850 Rev. A can't guarantee */
123 reg = memctl->memc_br0;
124 reg &= BR_PS_MSK; /* Clear everything except Port Size bits */
125 reg |= BR_V; /* then add just the "Bank Valid" bit */
126 memctl->memc_br0 = reg;
128 /* Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at
129 * preliminary addresses - these have to be modified later
130 * when FLASH size has been determined
132 * Depending on the size of the memory region defined by
133 * CONFIG_SYS_OR0_REMAP some boards (wide address mask) allow to map the
134 * CONFIG_SYS_MONITOR_BASE, while others (narrower address mask) can't
135 * map CONFIG_SYS_MONITOR_BASE.
137 * For example, for CONFIG_IVMS8, the CONFIG_SYS_MONITOR_BASE is
138 * 0xff000000, but CONFIG_SYS_OR0_REMAP's address mask is 0xfff80000.
140 * If BR0 wasn't loaded with address base 0xff000000, then BR0's
141 * base address remains as 0x00000000. However, the address mask
142 * have been narrowed to 512Kb, so CONFIG_SYS_MONITOR_BASE wasn't mapped
145 * This is why CONFIG_IVMS8 and similar boards must load BR0 with
146 * CONFIG_SYS_BR0_PRELIM in advance.
148 * [Thanks to Michael Liao for this explanation.
149 * I owe him a free beer. - wd]
152 #if defined(CONFIG_HERMES) || \
153 defined(CONFIG_ICU862) || \
154 defined(CONFIG_IP860) || \
155 defined(CONFIG_IVML24) || \
156 defined(CONFIG_IVMS8) || \
157 defined(CONFIG_LWMON) || \
158 defined(CONFIG_MHPC) || \
159 defined(CONFIG_PCU_E) || \
160 defined(CONFIG_R360MPI) || \
161 defined(CONFIG_RMU) || \
162 defined(CONFIG_RPXCLASSIC) || \
163 defined(CONFIG_RPXLITE) || \
164 defined(CONFIG_SPC1920) || \
165 defined(CONFIG_SPD823TS)
167 memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM;
170 #if defined(CONFIG_SYS_OR0_REMAP)
171 memctl->memc_or0 = CONFIG_SYS_OR0_REMAP;
173 #if defined(CONFIG_SYS_OR1_REMAP)
174 memctl->memc_or1 = CONFIG_SYS_OR1_REMAP;
176 #if defined(CONFIG_SYS_OR5_REMAP)
177 memctl->memc_or5 = CONFIG_SYS_OR5_REMAP;
180 /* now restrict to preliminary range */
181 memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM;
182 memctl->memc_or0 = CONFIG_SYS_OR0_PRELIM;
184 #if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
185 memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
186 memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
189 #if defined(CONFIG_IP860) /* disable CS0 now that Flash is mapped on CS1 */
190 memctl->memc_br0 = 0;
193 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
194 memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
195 memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
198 #if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
199 memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
200 memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
203 #if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
204 memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
205 memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
208 #if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
209 memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM;
210 memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM;
213 #if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
214 memctl->memc_or6 = CONFIG_SYS_OR6_PRELIM;
215 memctl->memc_br6 = CONFIG_SYS_BR6_PRELIM;
218 #if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
219 memctl->memc_or7 = CONFIG_SYS_OR7_PRELIM;
220 memctl->memc_br7 = CONFIG_SYS_BR7_PRELIM;
223 #endif /* ! CONFIG_MBX */
228 immr->im_cpm.cp_cpcr = CPM_CR_RST | CPM_CR_FLG;
229 do { /* Spin until command processed */
231 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
235 * on the MBX, things are a little bit different:
236 * - we need to read the VPD to get board information
237 * - the plprcr is set up dynamically
238 * - the memory controller is set up dynamically
241 #endif /* CONFIG_MBX */
243 #ifdef CONFIG_RPXCLASSIC
247 #if defined(CONFIG_RPXLITE) && defined(CONFIG_ENV_IS_IN_NVRAM)
251 #ifdef CONFIG_SYS_RCCR /* must be done before cpm_load_patch() */
252 /* write config value */
253 immr->im_cpm.cp_rccr = CONFIG_SYS_RCCR;
256 #if defined(CONFIG_SYS_I2C_UCODE_PATCH) || defined(CONFIG_SYS_SPI_UCODE_PATCH) || \
257 defined(CONFIG_SYS_SMC_UCODE_PATCH)
258 cpm_load_patch (immr); /* load mpc8xx microcode patch */
263 * initialize higher level parts of CPU like timers
265 int cpu_init_r (void)
267 #if defined(CONFIG_SYS_RTCSC) || defined(CONFIG_SYS_RMDS)
269 volatile immap_t *immr = (volatile immap_t *) (bd->bi_immr_base);
272 #ifdef CONFIG_SYS_RTCSC
273 /* Unlock RTSC register */
274 immr->im_sitk.sitk_rtcsck = KAPWR_KEY;
275 /* write config value */
276 immr->im_sit.sit_rtcsc = CONFIG_SYS_RTCSC;
279 #ifdef CONFIG_SYS_RMDS
280 /* write config value */
281 immr->im_cpm.cp_rmds = CONFIG_SYS_RMDS;