3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
13 #include <linux/compiler.h>
15 DECLARE_GLOBAL_DATA_PTR;
17 #if !defined(CONFIG_8xx_CONS_NONE) /* No Console at all */
19 #if defined(CONFIG_8xx_CONS_SMC1) /* Console on SMC1 */
21 #define PROFF_SMC PROFF_SMC1
22 #define CPM_CR_CH_SMC CPM_CR_CH_SMC1
24 #elif defined(CONFIG_8xx_CONS_SMC2) /* Console on SMC2 */
26 #define PROFF_SMC PROFF_SMC2
27 #define CPM_CR_CH_SMC CPM_CR_CH_SMC2
29 #endif /* CONFIG_8xx_CONS_SMCx */
31 #if defined(CONFIG_8xx_CONS_SCC1) /* Console on SCC1 */
33 #define PROFF_SCC PROFF_SCC1
34 #define CPM_CR_CH_SCC CPM_CR_CH_SCC1
36 #elif defined(CONFIG_8xx_CONS_SCC2) /* Console on SCC2 */
38 #define PROFF_SCC PROFF_SCC2
39 #define CPM_CR_CH_SCC CPM_CR_CH_SCC2
41 #elif defined(CONFIG_8xx_CONS_SCC3) /* Console on SCC3 */
43 #define PROFF_SCC PROFF_SCC3
44 #define CPM_CR_CH_SCC CPM_CR_CH_SCC3
46 #elif defined(CONFIG_8xx_CONS_SCC4) /* Console on SCC4 */
48 #define PROFF_SCC PROFF_SCC4
49 #define CPM_CR_CH_SCC CPM_CR_CH_SCC4
51 #endif /* CONFIG_8xx_CONS_SCCx */
53 #if !defined(CONFIG_SYS_SMC_RXBUFLEN)
54 #define CONFIG_SYS_SMC_RXBUFLEN 1
55 #define CONFIG_SYS_MAXIDLE 0
57 #if !defined(CONFIG_SYS_MAXIDLE)
58 #error "you must define CONFIG_SYS_MAXIDLE"
62 typedef volatile struct serialbuffer {
63 cbd_t rxbd; /* Rx BD */
64 cbd_t txbd; /* Tx BD */
65 uint rxindex; /* index for next character to read */
66 volatile uchar rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */
67 volatile uchar txbuf; /* tx buffers */
70 static void serial_setdivisor(volatile cpm8xx_t *cp)
72 int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate;
74 if(divisor/16>0x1000) {
75 /* bad divisor, assume 50MHz clock and 9600 baud */
76 divisor=(50*1000*1000 + 8*9600)/16/9600;
79 #ifdef CONFIG_SYS_BRGCLK_PRESCALE
80 divisor /= CONFIG_SYS_BRGCLK_PRESCALE;
84 cp->cp_brgc1=((divisor-1)<<1) | CPM_BRG_EN;
86 cp->cp_brgc1=((divisor/16-1)<<1) | CPM_BRG_EN | CPM_BRG_DIV16;
90 #if (defined (CONFIG_8xx_CONS_SMC1) || defined (CONFIG_8xx_CONS_SMC2))
93 * Minimal serial functions needed to use one of the SMC ports
94 * as serial console interface.
97 static void smc_setbrg (void)
99 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
100 volatile cpm8xx_t *cp = &(im->im_cpm);
102 /* Set up the baud rate generator.
103 * See 8xx_io/commproc.c for details.
108 cp->cp_simode = 0x00000000;
110 serial_setdivisor(cp);
113 static int smc_init (void)
115 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
117 volatile smc_uart_t *up;
118 volatile cpm8xx_t *cp = &(im->im_cpm);
119 #if (!defined(CONFIG_8xx_CONS_SMC1)) && (defined(CONFIG_MPC823) || defined(CONFIG_MPC850))
120 volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
123 volatile serialbuffer_t *rtx;
125 /* initialize pointers to SMC */
127 sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]);
128 up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC];
129 #ifdef CONFIG_SYS_SMC_UCODE_PATCH
130 up = (smc_uart_t *) &cp->cp_dpmem[up->smc_rpbase];
132 /* Disable relocation */
136 /* Disable transmitter/receiver. */
137 sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
140 im->im_siu_conf.sc_sdcr = 1;
142 /* clear error conditions */
143 #ifdef CONFIG_SYS_SDSR
144 im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR;
146 im->im_sdma.sdma_sdsr = 0x83;
149 /* clear SDMA interrupt mask */
150 #ifdef CONFIG_SYS_SDMR
151 im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR;
153 im->im_sdma.sdma_sdmr = 0x00;
156 #if defined(CONFIG_8xx_CONS_SMC1)
157 /* Use Port B for SMC1 instead of other functions. */
158 cp->cp_pbpar |= 0x000000c0;
159 cp->cp_pbdir &= ~0x000000c0;
160 cp->cp_pbodr &= ~0x000000c0;
161 #else /* CONFIG_8xx_CONS_SMC2 */
162 # if defined(CONFIG_MPC823) || defined(CONFIG_MPC850)
163 /* Use Port A for SMC2 instead of other functions. */
164 ip->iop_papar |= 0x00c0;
165 ip->iop_padir &= ~0x00c0;
166 ip->iop_paodr &= ~0x00c0;
167 # else /* must be a 860 then */
168 /* Use Port B for SMC2 instead of other functions.
170 cp->cp_pbpar |= 0x00000c00;
171 cp->cp_pbdir &= ~0x00000c00;
172 cp->cp_pbodr &= ~0x00000c00;
176 /* Set the physical address of the host memory buffers in
177 * the buffer descriptors.
180 #ifdef CONFIG_SYS_ALLOC_DPRAM
182 * size of struct serialbuffer with bd rx/tx, buffer rx/tx and rx index
184 dpaddr = dpram_alloc_align((sizeof(serialbuffer_t)), 8);
186 dpaddr = CPM_SERIAL_BASE ;
189 rtx = (serialbuffer_t *)&cp->cp_dpmem[dpaddr];
190 /* Allocate space for two buffer descriptors in the DP ram.
191 * For now, this address seems OK, but it may have to
192 * change with newer versions of the firmware.
193 * damm: allocating space after the two buffers for rx/tx data
196 rtx->rxbd.cbd_bufaddr = (uint) &rtx->rxbuf;
197 rtx->rxbd.cbd_sc = 0;
199 rtx->txbd.cbd_bufaddr = (uint) &rtx->txbuf;
200 rtx->txbd.cbd_sc = 0;
202 /* Set up the uart parameters in the parameter ram. */
203 up->smc_rbase = dpaddr;
204 up->smc_tbase = dpaddr+sizeof(cbd_t);
205 up->smc_rfcr = SMC_EB;
206 up->smc_tfcr = SMC_EB;
207 #if defined (CONFIG_SYS_SMC_UCODE_PATCH)
208 up->smc_rbptr = up->smc_rbase;
209 up->smc_tbptr = up->smc_tbase;
214 /* Set UART mode, 8 bit, no parity, one stop.
215 * Enable receive and transmit.
217 sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
219 /* Mask all interrupts and remove anything pending.
224 #ifdef CONFIG_SYS_SPC1920_SMC1_CLK4
225 /* clock source is PLD */
227 /* set freq to 19200 Baud */
228 *((volatile uchar *) CONFIG_SYS_SPC1920_PLD_BASE+6) = 0x3;
229 /* configure clk4 as input */
230 im->im_ioport.iop_pdpar |= 0x800;
231 im->im_ioport.iop_pddir &= ~0x800;
233 cp->cp_simode = ((cp->cp_simode & ~0xf000) | 0x7000);
235 /* Set up the baud rate generator */
239 /* Make the first buffer the only buffer. */
240 rtx->txbd.cbd_sc |= BD_SC_WRAP;
241 rtx->rxbd.cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
243 /* single/multi character receive. */
244 up->smc_mrblr = CONFIG_SYS_SMC_RXBUFLEN;
245 up->smc_maxidl = CONFIG_SYS_MAXIDLE;
248 /* Initialize Tx/Rx parameters. */
249 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
252 cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
254 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
257 /* Enable transmitter/receiver. */
258 sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
264 smc_putc(const char c)
266 volatile smc_uart_t *up;
267 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
268 volatile cpm8xx_t *cpmp = &(im->im_cpm);
269 volatile serialbuffer_t *rtx;
274 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
275 #ifdef CONFIG_SYS_SMC_UCODE_PATCH
276 up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
279 rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];
281 /* Wait for last character to go. */
283 rtx->txbd.cbd_datlen = 1;
284 rtx->txbd.cbd_sc |= BD_SC_READY;
287 while (rtx->txbd.cbd_sc & BD_SC_READY) {
294 smc_puts (const char *s)
304 volatile smc_uart_t *up;
305 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
306 volatile cpm8xx_t *cpmp = &(im->im_cpm);
307 volatile serialbuffer_t *rtx;
310 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
311 #ifdef CONFIG_SYS_SMC_UCODE_PATCH
312 up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
314 rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];
316 /* Wait for character to show up. */
317 while (rtx->rxbd.cbd_sc & BD_SC_EMPTY)
320 /* the characters are read one by one,
321 * use the rxindex to know the next char to deliver
323 c = *(unsigned char *) (rtx->rxbd.cbd_bufaddr+rtx->rxindex);
326 /* check if all char are readout, then make prepare for next receive */
327 if (rtx->rxindex >= rtx->rxbd.cbd_datlen) {
329 rtx->rxbd.cbd_sc |= BD_SC_EMPTY;
337 volatile smc_uart_t *up;
338 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
339 volatile cpm8xx_t *cpmp = &(im->im_cpm);
340 volatile serialbuffer_t *rtx;
342 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
343 #ifdef CONFIG_SYS_SMC_UCODE_PATCH
344 up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
347 rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];
349 return !(rtx->rxbd.cbd_sc & BD_SC_EMPTY);
352 struct serial_device serial_smc_device =
354 .name = "serial_smc",
357 .setbrg = smc_setbrg,
364 #endif /* CONFIG_8xx_CONS_SMC1 || CONFIG_8xx_CONS_SMC2 */
366 #if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \
367 defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
372 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
373 volatile cpm8xx_t *cp = &(im->im_cpm);
375 /* Set up the baud rate generator.
376 * See 8xx_io/commproc.c for details.
381 cp->cp_sicr &= ~(0x000000FF << (8 * SCC_INDEX));
383 serial_setdivisor(cp);
386 static int scc_init (void)
388 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
390 volatile scc_uart_t *up;
391 volatile cbd_t *tbdf, *rbdf;
392 volatile cpm8xx_t *cp = &(im->im_cpm);
394 #if (SCC_INDEX != 2) || !defined(CONFIG_MPC850)
395 volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
398 /* initialize pointers to SCC */
400 sp = (scc_t *) &(cp->cp_scc[SCC_INDEX]);
401 up = (scc_uart_t *) &cp->cp_dparam[PROFF_SCC];
403 /* Disable transmitter/receiver. */
404 sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
406 #if (SCC_INDEX == 2) && defined(CONFIG_MPC850)
408 * The MPC850 has SCC3 on Port B
410 cp->cp_pbpar |= 0x06;
411 cp->cp_pbdir &= ~0x06;
412 cp->cp_pbodr &= ~0x06;
414 #elif (SCC_INDEX < 2)
416 * Standard configuration for SCC's is on Part A
418 ip->iop_papar |= ((3 << (2 * SCC_INDEX)));
419 ip->iop_padir &= ~((3 << (2 * SCC_INDEX)));
420 ip->iop_paodr &= ~((3 << (2 * SCC_INDEX)));
423 /* Allocate space for two buffer descriptors in the DP ram. */
425 #ifdef CONFIG_SYS_ALLOC_DPRAM
426 dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
428 dpaddr = CPM_SERIAL2_BASE ;
432 im->im_siu_conf.sc_sdcr = 0x0001;
434 /* Set the physical address of the host memory buffers in
435 * the buffer descriptors.
438 rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
439 rbdf->cbd_bufaddr = (uint) (rbdf+2);
442 tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
445 /* Set up the baud rate generator. */
448 /* Set up the uart parameters in the parameter ram. */
449 up->scc_genscc.scc_rbase = dpaddr;
450 up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
452 /* Initialize Tx/Rx parameters. */
453 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
455 cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
457 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
460 up->scc_genscc.scc_rfcr = SCC_EB | 0x05;
461 up->scc_genscc.scc_tfcr = SCC_EB | 0x05;
463 up->scc_genscc.scc_mrblr = 1; /* Single character receive */
464 up->scc_maxidl = 0; /* disable max idle */
465 up->scc_brkcr = 1; /* send one break character on stop TX */
473 up->scc_char1 = 0x8000;
474 up->scc_char2 = 0x8000;
475 up->scc_char3 = 0x8000;
476 up->scc_char4 = 0x8000;
477 up->scc_char5 = 0x8000;
478 up->scc_char6 = 0x8000;
479 up->scc_char7 = 0x8000;
480 up->scc_char8 = 0x8000;
481 up->scc_rccm = 0xc0ff;
483 /* Set low latency / small fifo. */
484 sp->scc_gsmrh = SCC_GSMRH_RFW;
486 /* Set SCC(x) clock mode to 16x
487 * See 8xx_io/commproc.c for details.
492 /* Set UART mode, clock divider 16 on Tx and Rx */
493 sp->scc_gsmrl &= ~0xF;
495 (SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
498 sp->scc_psmr |= SCU_PSMR_CL;
500 /* Mask all interrupts and remove anything pending. */
502 sp->scc_scce = 0xffff;
503 sp->scc_dsr = 0x7e7e;
504 sp->scc_psmr = 0x3000;
506 /* Make the first buffer the only buffer. */
507 tbdf->cbd_sc |= BD_SC_WRAP;
508 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
510 /* Enable transmitter/receiver. */
511 sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
517 scc_putc(const char c)
519 volatile cbd_t *tbdf;
521 volatile scc_uart_t *up;
522 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
523 volatile cpm8xx_t *cpmp = &(im->im_cpm);
528 up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
530 tbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_tbase];
532 /* Wait for last character to go. */
534 buf = (char *)tbdf->cbd_bufaddr;
537 tbdf->cbd_datlen = 1;
538 tbdf->cbd_sc |= BD_SC_READY;
541 while (tbdf->cbd_sc & BD_SC_READY) {
548 scc_puts (const char *s)
558 volatile cbd_t *rbdf;
559 volatile unsigned char *buf;
560 volatile scc_uart_t *up;
561 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
562 volatile cpm8xx_t *cpmp = &(im->im_cpm);
565 up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
567 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
569 /* Wait for character to show up. */
570 buf = (unsigned char *)rbdf->cbd_bufaddr;
572 while (rbdf->cbd_sc & BD_SC_EMPTY)
576 rbdf->cbd_sc |= BD_SC_EMPTY;
584 volatile cbd_t *rbdf;
585 volatile scc_uart_t *up;
586 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
587 volatile cpm8xx_t *cpmp = &(im->im_cpm);
589 up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
591 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
593 return(!(rbdf->cbd_sc & BD_SC_EMPTY));
596 struct serial_device serial_scc_device =
598 .name = "serial_scc",
601 .setbrg = scc_setbrg,
608 #endif /* CONFIG_8xx_CONS_SCCx */
610 __weak struct serial_device *default_serial_console(void)
612 #if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2)
613 return &serial_smc_device;
615 return &serial_scc_device;
619 void mpc8xx_serial_initialize(void)
621 #if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2)
622 serial_register(&serial_smc_device);
624 #if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \
625 defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
626 serial_register(&serial_scc_device);
630 #if defined(CONFIG_CMD_KGDB)
633 kgdb_serial_init(void)
637 if (strcmp(default_serial_console()->name, "serial_smc") == 0)
639 #if defined(CONFIG_8xx_CONS_SMC1)
641 #elif defined(CONFIG_8xx_CONS_SMC2)
645 else if (strcmp(default_serial_console()->name, "serial_scc") == 0)
647 #if defined(CONFIG_8xx_CONS_SCC1)
649 #elif defined(CONFIG_8xx_CONS_SCC2)
651 #elif defined(CONFIG_8xx_CONS_SCC3)
653 #elif defined(CONFIG_8xx_CONS_SCC4)
660 serial_printf("[on %s%d] ", default_serial_console()->name, i);
671 putDebugStr (const char *str)
679 return serial_getc();
683 kgdb_interruptible (int yes)
689 #endif /* CONFIG_8xx_CONS_NONE */